patches/0021-ENGR00113611-Add-FEC-support-for-BBG2.patch

   1 From 23b6527003ca6a12d7872e9e552160041d8b6285 Mon Sep 17 00:00:00 2001
   2 From: Terry Lv <r65388@freescale.com>
   3 Date: Wed, 24 Jun 2009 11:31:38 +0800
   4 Subject: [PATCH] ENGR00113611: Add FEC support for BBG2.
   5
   6 Add FEC support for BBG2.
   7
   8 Signed-off-by: Terry Lv <r65388@freescale.com>
   9 ---
  10  board/freescale/imx51/imx51.c    |  255 +++++++++++++++++++++++++++++++-------
  11  cpu/arm_cortexa8/mx51/generic.c  |   25 ++++
  12  drivers/mmc/fsl_mmc.c            |    2 +
  13  drivers/net/mxc_fec.c            |   13 +-
  14  drivers/spi/imx_spi_pmic.c       |   14 ++-
  15  include/asm-arm/arch-mx51/mx51.h |    1 +
  16  include/configs/imx51.h          |   35 +++++-
  17  net/eth.c                        |    5 +
  18  8 files changed, 289 insertions(+), 61 deletions(-)
  19
  20 diff --git a/board/freescale/imx51/imx51.c b/board/freescale/imx51/imx51.c
  21 index b0bbf46..5c3c022 100644
  22 --- a/board/freescale/imx51/imx51.c
  23 +++ b/board/freescale/imx51/imx51.c
  24 @@ -24,13 +24,14 @@
  25
  26  #include <common.h>
  27  #include <asm/io.h>
  28 -#include <asm/errno.h>
  29  #include <asm/arch/mx51.h>
  30  #include <asm/arch/mx51_pins.h>
  31  #include <asm/arch/iomux.h>
  32 +#include <asm/errno.h>
  33  #include <i2c.h>
  34  #include "board-imx51.h"
  35  #include <asm/arch/imx_spi.h>
  36 +#include <asm/arch/imx_spi_pmic.h>
  37
  38  DECLARE_GLOBAL_DATA_PTR;
  39
  40 @@ -158,48 +159,6 @@ static void setup_expio(void)
  41         writew(reg, mx51_io_base_addr + PBC_SW_RESET);
  42  }
  43
  44 -int board_init(void)
  45 -{
  46 -       setup_soc_rev();
  47 -
  48 -       gd->bd->bi_arch_number = MACH_TYPE_MX51_3DS;    /* board id for linux */
  49 -       /* address of boot parameters */
  50 -       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  51 -
  52 -       setup_uart();
  53 -       setup_nfc();
  54 -       setup_expio();
  55 -       return 0;
  56 -}
  57 -
  58 -#ifdef BOARD_LATE_INIT
  59 -int board_late_init(void)
  60 -{
  61 -       return 0;
  62 -}
  63 -#endif
  64 -
  65 -int checkboard(void)
  66 -{
  67 -       printf("Board: MX51 3STACK [");
  68 -       switch (__REG(SRC_BASE_ADDR + 0x8)) {
  69 -       case 0x0001:
  70 -               printf("POR");
  71 -               break;
  72 -       case 0x0009:
  73 -               printf("RST");
  74 -               break;
  75 -       case 0x0010:
  76 -       case 0x0011:
  77 -               printf("WDOG");
  78 -               break;
  79 -       default:
  80 -               printf("unknown");
  81 -       }
  82 -       printf("]\n");
  83 -       return 0;
  84 -}
  85 -
  86  void spi_io_init(struct imx_spi_dev_t *dev)
  87  {
  88         switch (dev->base) {
  89 @@ -242,13 +201,177 @@ void spi_io_init(struct imx_spi_dev_t *dev)
  90         }
  91  }
  92
  93 +static void setup_fec(void)
  94 +{
  95 +       /*FEC_MDIO*/
  96 +       writel(0x3, IOMUXC_BASE_ADDR + 0x0D4);
  97 +       writel(0x1FD, IOMUXC_BASE_ADDR + 0x0468);
  98 +       writel(0x0, IOMUXC_BASE_ADDR + 0x0954);
  99 +
 100 +       /*FEC_MDC*/
 101 +       writel(0x2, IOMUXC_BASE_ADDR + 0x13C);
 102 +       writel(0x2004, IOMUXC_BASE_ADDR + 0x0524);
 103 +
 104 +       /* FEC RDATA[3] */
 105 +       writel(0x3, IOMUXC_BASE_ADDR + 0x0EC);
 106 +       writel(0x180, IOMUXC_BASE_ADDR + 0x0480);
 107 +       writel(0x0, IOMUXC_BASE_ADDR + 0x0964);
 108 +
 109 +       /* FEC RDATA[2] */
 110 +       writel(0x3, IOMUXC_BASE_ADDR + 0x0E8);
 111 +       writel(0x180, IOMUXC_BASE_ADDR + 0x047C);
 112 +       writel(0x0, IOMUXC_BASE_ADDR + 0x0960);
 113 +
 114 +       /* FEC RDATA[1] */
 115 +       writel(0x3, IOMUXC_BASE_ADDR + 0x0d8);
 116 +       writel(0x180, IOMUXC_BASE_ADDR + 0x046C);
 117 +       writel(0x0, IOMUXC_BASE_ADDR + 0x095C);
 118 +
 119 +       /* FEC RDATA[0] */
 120 +       writel(0x2, IOMUXC_BASE_ADDR + 0x016C);
 121 +       writel(0x2180, IOMUXC_BASE_ADDR + 0x0554);
 122 +       writel(0x0, IOMUXC_BASE_ADDR + 0x0958);
 123 +
 124 +       /* FEC TDATA[3] */
 125 +       writel(0x2, IOMUXC_BASE_ADDR + 0x148);
 126 +       writel(0x2004, IOMUXC_BASE_ADDR + 0x0530);
 127 +
 128 +       /* FEC TDATA[2] */
 129 +       writel(0x2, IOMUXC_BASE_ADDR + 0x144);
 130 +       writel(0x2004, IOMUXC_BASE_ADDR + 0x052C);
 131 +
 132 +       /* FEC TDATA[1] */
 133 +       writel(0x2, IOMUXC_BASE_ADDR + 0x140);
 134 +       writel(0x2004, IOMUXC_BASE_ADDR + 0x0528);
 135 +
 136 +       /* FEC TDATA[0] */
 137 +       writel(0x2, IOMUXC_BASE_ADDR + 0x0170);
 138 +       writel(0x2004, IOMUXC_BASE_ADDR + 0x0558);
 139 +
 140 +       /* FEC TX_EN */
 141 +       writel(0x1, IOMUXC_BASE_ADDR + 0x014C);
 142 +       writel(0x2004, IOMUXC_BASE_ADDR + 0x0534);
 143 +
 144 +       /* FEC TX_ER */
 145 +       writel(0x2, IOMUXC_BASE_ADDR + 0x0138);
 146 +       writel(0x2004, IOMUXC_BASE_ADDR + 0x0520);
 147 +
 148 +       /* FEC TX_CLK */
 149 +       writel(0x1, IOMUXC_BASE_ADDR + 0x0150);
 150 +       writel(0x2180, IOMUXC_BASE_ADDR + 0x0538);
 151 +       writel(0x0, IOMUXC_BASE_ADDR + 0x0974);
 152 +
 153 +       /* FEC COL */
 154 +       writel(0x1, IOMUXC_BASE_ADDR + 0x0124);
 155 +       writel(0x2180, IOMUXC_BASE_ADDR + 0x0500);
 156 +       writel(0x0, IOMUXC_BASE_ADDR + 0x094c);
 157 +
 158 +       /* FEC RX_CLK */
 159 +       writel(0x1, IOMUXC_BASE_ADDR + 0x0128);
 160 +       writel(0x2180, IOMUXC_BASE_ADDR + 0x0504);
 161 +       writel(0x0, IOMUXC_BASE_ADDR + 0x0968);
 162 +
 163 +       /* FEC CRS */
 164 +       writel(0x3, IOMUXC_BASE_ADDR + 0x0f4);
 165 +       writel(0x180, IOMUXC_BASE_ADDR + 0x0488);
 166 +       writel(0x0, IOMUXC_BASE_ADDR + 0x0950);
 167 +
 168 +       /* FEC RX_ER */
 169 +       writel(0x3, IOMUXC_BASE_ADDR + 0x0f0);
 170 +       writel(0x180, IOMUXC_BASE_ADDR + 0x0484);
 171 +       writel(0x0, IOMUXC_BASE_ADDR + 0x0970);
 172 +
 173 +       /* FEC RX_DV */
 174 +       writel(0x2, IOMUXC_BASE_ADDR + 0x164);
 175 +       writel(0x2180, IOMUXC_BASE_ADDR + 0x054C);
 176 +       writel(0x0, IOMUXC_BASE_ADDR + 0x096C);
 177 +}
 178 +
 179 +static void power_init(void)
 180 +{
 181 +       struct spi_slave *slave;
 182 +       unsigned int val;
 183 +       unsigned int reg;
 184 +
 185 +       slave = spi_pmic_probe();
 186 +
 187 +       /* power up the system first */
 188 +       pmic_reg(slave, 34, 0x00200000, 1);
 189 +
 190 +       if (mxc_get_clock(MXC_FEC_CLK) > 800000000) {
 191 +               /* Set core voltage to 1.175V */
 192 +               val = pmic_reg(slave, 24, 0, 0);
 193 +               val = (val & (~0x1F)) | 0x17;
 194 +               pmic_reg(slave, 24, val, 1);
 195 +       }
 196 +
 197 +       /* Setup VCC (SW2) to 1.225 */
 198 +       val = pmic_reg(slave, 25, 0, 0);
 199 +       val = (val & (~0x1F)) | 0x19;
 200 +       pmic_reg(slave, 25, val, 1);
 201 +
 202 +       /* Setup 1V2_DIG1 (SW3) to 1.2 */
 203 +       val = pmic_reg(slave, 26, 0, 0);
 204 +       val = (val & (~0x1F)) | 0x18;
 205 +       pmic_reg(slave, 25, val, 1);
 206 +
 207 +       /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
 208 +       val = pmic_reg(slave, 30, 0, 0);
 209 +       val &= ~0x34030;
 210 +       val |= 0x10020;
 211 +       pmic_reg(slave, 30, val, 1);
 212 +
 213 +       /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
 214 +       val = pmic_reg(slave, 31, 0, 0);
 215 +       val &= ~0x1FC;
 216 +       val |= 0x1F4;
 217 +       pmic_reg(slave, 31, val, 1);
 218 +
 219 +       /* Configure VGEN3 and VCAM regulators to use external PNP */
 220 +       val = 0x208;
 221 +       pmic_reg(slave, 33, val, 1);
 222 +       udelay(200);
 223 +
 224 +       reg = readl(GPIO2_BASE_ADDR + 0x0);
 225 +       reg &= ~0x4000;  /* Lower reset line */
 226 +       writel(reg, GPIO2_BASE_ADDR + 0x0);
 227 +
 228 +       reg = readl(GPIO2_BASE_ADDR + 0x4);
 229 +       reg |= 0x4000;  /* configure GPIO lines as output */
 230 +       writel(reg, GPIO2_BASE_ADDR + 0x4);
 231 +
 232 +       /* Reset the ethernet controller over GPIO */
 233 +       writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
 234 +
 235 +       /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 236 +       val = 0x49249;
 237 +       pmic_reg(slave, 33, val, 1);
 238 +
 239 +       udelay(500);
 240 +
 241 +       reg = readl(GPIO2_BASE_ADDR + 0x0);
 242 +       reg |= 0x4000;
 243 +       writel(reg, GPIO2_BASE_ADDR + 0x0);
 244 +
 245 +       /* Setup the FEC after enabling the regulators */
 246 +       setup_fec();
 247 +
 248 +       spi_pmic_free(slave);
 249 +}
 250 +
 251  #ifdef CONFIG_NET_MULTI
 252 +
 253 +#if defined(CONFIG_DRIVER_SMC911X)
 254 +extern int smc911x_initialize(bd_t *bis);
 255 +#endif
 256  int board_eth_init(bd_t *bis)
 257  {
 258         int rc = -ENODEV;
 259 +
 260  #if defined(CONFIG_DRIVER_SMC911X)
 261 -        rc = smc911x_initialize(bis);
 262 +       rc = smc911x_initialize(bis);
 263  #endif
 264 +
 265         return rc;
 266  }
 267  #endif
 268 @@ -329,3 +452,47 @@ int sdhc_init(void)
 269  }
 270
 271  #endif
 272 +
 273 +int board_init(void)
 274 +{
 275 +       setup_soc_rev();
 276 +
 277 +       gd->bd->bi_arch_number = MACH_TYPE_MX51_3DS;    /* board id for linux */
 278 +       /* address of boot parameters */
 279 +       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 280 +
 281 +       setup_uart();
 282 +       setup_nfc();
 283 +       setup_expio();
 284 +       return 0;
 285 +}
 286 +
 287 +#ifdef BOARD_LATE_INIT
 288 +int board_late_init(void)
 289 +{
 290 +       power_init();
 291 +       return 0;
 292 +}
 293 +#endif
 294 +
 295 +int checkboard(void)
 296 +{
 297 +       printf("Board: MX51 3STACK [");
 298 +       switch (__REG(SRC_BASE_ADDR + 0x8)) {
 299 +       case 0x0001:
 300 +               printf("POR");
 301 +               break;
 302 +       case 0x0009:
 303 +               printf("RST");
 304 +               break;
 305 +       case 0x0010:
 306 +       case 0x0011:
 307 +               printf("WDOG");
 308 +               break;
 309 +       default:
 310 +               printf("unknown");
 311 +       }
 312 +       printf("]\n");
 313 +       return 0;
 314 +}
 315 +
 316 diff --git a/cpu/arm_cortexa8/mx51/generic.c b/cpu/arm_cortexa8/mx51/generic.c
 317 index ef8ef98..6f928f6 100644
 318 --- a/cpu/arm_cortexa8/mx51/generic.c
 319 +++ b/cpu/arm_cortexa8/mx51/generic.c
 320 @@ -25,6 +25,7 @@
 321
 322  #include <common.h>
 323  #include <asm/arch/mx51.h>
 324 +#include <asm/errno.h>
 325  #include "crm_regs.h"
 326
 327  enum pll_clocks {
 328 @@ -203,6 +204,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 329                 return __get_uart_clk();
 330         case MXC_CSPI_CLK:
 331                 return __get_cspi_clk();
 332 +       case MXC_FEC_CLK:
 333 +               return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
 334 +       default:
 335 +               break;
 336         }
 337         return -1;
 338  }
 339 @@ -233,3 +238,23 @@ int print_cpuinfo(void)
 340         return 0;
 341  }
 342  #endif
 343 +
 344 +/*
 345 + * Initializes on-chip ethernet controllers.
 346 + * to override, implement board_eth_init()
 347 + */
 348 + #if defined(CONFIG_MXC_FEC)
 349 + extern int mxc_fec_initialize(bd_t *bis);
 350 + #endif
 351 +
 352 +int cpu_eth_init(bd_t *bis)
 353 +{
 354 +       int rc = -ENODEV;
 355 +
 356 +#if defined(CONFIG_MXC_FEC)
 357 +       rc = mxc_fec_initialize(bis);
 358 +#endif
 359 +
 360 +       return rc;
 361 +}
 362 +
 363 diff --git a/drivers/mmc/fsl_mmc.c b/drivers/mmc/fsl_mmc.c
 364 index 2fbf4d6..85829d0 100644
 365 --- a/drivers/mmc/fsl_mmc.c
 366 +++ b/drivers/mmc/fsl_mmc.c
 367 @@ -38,6 +38,8 @@
 368  #define RETRY_TIMEOUT                                  (10)
 369
 370
 371 +extern int sdhc_init();
 372 +
 373  extern int fat_register_device(block_dev_desc_t *dev_desc, int part_no);
 374
 375  static block_dev_desc_t        mmc_dev;
 376 diff --git a/drivers/net/mxc_fec.c b/drivers/net/mxc_fec.c
 377 index 218c432..91d248b 100644
 378 --- a/drivers/net/mxc_fec.c
 379 +++ b/drivers/net/mxc_fec.c
 380 @@ -121,7 +121,7 @@ static inline void fec_localhw_setup(volatile fec_t *fecp)
 381         fecp->fec_miigsk_enr = FEC_MIIGSK_ENR_EN;
 382  }
 383  #else
 384 -static inline void fec_localhw_setup(struct fec_t *fecp)
 385 +static inline void fec_localhw_setup(fec_t *fecp)
 386  {
 387  }
 388  #endif
 389 @@ -271,7 +271,7 @@ static inline u16 getFecPhyStatus(volatile fec_t *fecp, unsigned char addr)
 390         return val;
 391  }
 392
 393 -static void setFecDuplexSpeed(volatile fec_t *fecp, unsigned char addr,
 394 +static void setFecDuplexSpeed(volatile fec_t *fecp,  unsigned char addr,
 395                               int dup_spd)
 396  {
 397         unsigned short val;
 398 @@ -386,7 +386,7 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
 399                 j++;
 400         }
 401         if (j >= FEC_MAX_TIMEOUT)
 402 -               printf("TX timeout packet at %x\n", packet);
 403 +               printf("TX timeout packet at %p\n", packet);
 404
 405  #ifdef ET_DEBUG
 406         printf("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
 407 @@ -612,7 +612,7 @@ int fec_init(struct eth_device *dev, bd_t *bd)
 408
 409         fec_reset(dev);
 410
 411 -       fec_localhw_setup(fecp);
 412 +       fec_localhw_setup((fec_t *)fecp);
 413
 414  #if defined (CONFIG_CMD_MII) || defined (CONFIG_MII) || \
 415         defined (CONFIG_DISCOVER_PHY)
 416 @@ -622,10 +622,11 @@ int fec_init(struct eth_device *dev, bd_t *bd)
 417         if (info->phy_addr < 0 || info->phy_addr > 0x1F)
 418                 info->phy_addr = mxc_fec_mii_discover_phy(dev);
 419  #endif
 420 -       setFecDuplexSpeed(fecp, bd, info->dup_spd);
 421 +       setFecDuplexSpeed(fecp, (unsigned char)bd, info->dup_spd);
 422  #else
 423  #ifndef CONFIG_DISCOVER_PHY
 424 -       setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
 425 +       setFecDuplexSpeed(fecp, (unsigned char)bd,
 426 +                               (FECDUPLEX << 16) | FECSPEED);
 427  #endif                         /* ifndef CONFIG_SYS_DISCOVER_PHY */
 428  #endif                         /* CONFIG_CMD_MII || CONFIG_MII */
 429
 430 diff --git a/drivers/spi/imx_spi_pmic.c b/drivers/spi/imx_spi_pmic.c
 431 index bce42c2..79d798d 100644
 432 --- a/drivers/spi/imx_spi_pmic.c
 433 +++ b/drivers/spi/imx_spi_pmic.c
 434 @@ -53,13 +53,17 @@ u32 pmic_reg(struct spi_slave *slave, u32 reg, u32 val, u32 write)
 435         pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF);
 436         printf("reg=0x%x, val=0x%08x\n", reg, pmic_tx);
 437
 438 -       spi_xfer(slave, 4 << 3, (u8 *)&pmic_tx,
 439 -                                 (u8 *)&pmic_rx, 0);
 440 +       if (spi_xfer(slave, 4 << 3, (u8 *)&pmic_tx, (u8 *)&pmic_rx,
 441 +                       SPI_XFER_BEGIN | SPI_XFER_END)) {
 442 +               return -1;
 443 +       }
 444
 445         if (write) {
 446                 pmic_tx &= ~(1 << 31);
 447 -               spi_xfer(slave, 4 << 3,
 448 -                       (u8 *)&pmic_tx, (u8 *)&pmic_rx, 0);
 449 +               if (spi_xfer(slave, 4 << 3, (u8 *)&pmic_tx, (u8 *)&pmic_rx,
 450 +                       SPI_XFER_BEGIN | SPI_XFER_END)) {
 451 +                       return -1;
 452 +               }
 453         }
 454
 455         return pmic_rx;
 456 @@ -73,7 +77,7 @@ void show_pmic_info(struct spi_slave *slave)
 457                 return;
 458
 459         rev_id = pmic_reg(slave, 7, 0, 0);
 460 -       printf("PMIC ID: 0x%08x [Rev: ", rev_id);
 461 +       debug("PMIC ID: 0x%08x [Rev: ", rev_id);
 462         switch (rev_id & 0x1F) {
 463         case 0x1:
 464                 printf("1.0");
 465 diff --git a/include/asm-arm/arch-mx51/mx51.h b/include/asm-arm/arch-mx51/mx51.h
 466 index 29120ab..14c2b2d 100644
 467 --- a/include/asm-arm/arch-mx51/mx51.h
 468 +++ b/include/asm-arm/arch-mx51/mx51.h
 469 @@ -405,6 +405,7 @@ MXC_IPG_CLK,
 470  MXC_IPG_PERCLK,
 471  MXC_UART_CLK,
 472  MXC_CSPI_CLK,
 473 +MXC_FEC_CLK,
 474  };
 475
 476  extern unsigned int mxc_get_clock(enum mxc_clock clk);
 477 diff --git a/include/configs/imx51.h b/include/configs/imx51.h
 478 index 7bd6c38..3257843 100644
 479 --- a/include/configs/imx51.h
 480 +++ b/include/configs/imx51.h
 481 @@ -91,15 +91,33 @@
 482  #define CONFIG_CMD_MMC
 483  #define CONFIG_DOS_PARTITION   1
 484  #define CONFIG_CMD_FAT         1
 485 +#define CONFIG_MMC_BASE         0x0
 486 +
 487 +/*
 488 + * Eth Configs
 489 + */
 490 +#define CONFIG_HAS_ETH1
 491 +#define CONFIG_NET_MULTI 1
 492 +#define CONFIG_MXC_FEC
 493 +#define CONFIG_MII
 494 +#define CONFIG_DISCOVER_PHY
 495 +
 496 +#define CONFIG_FEC0_IOBASE     FEC_BASE_ADDR
 497 +#define CONFIG_FEC0_PINMUX     -1
 498 +#define CONFIG_FEC0_PHY_ADDR   0x1F
 499 +#define CONFIG_FEC0_MIIBASE    -1
 500 +
 501 +#define CONFIG_CMD_PING
 502 +#define CONFIG_CMD_DHCP
 503 +#define CONFIG_CMD_MII
 504 +#define CONFIG_CMD_NET
 505
 506  /* allow to overwrite serial and ethaddr */
 507  #define CONFIG_ENV_OVERWRITE
 508 -#define CONFIG_CONS_INDEX      1
 509 -#define CONFIG_BAUDRATE                115200
 510 +#define CONFIG_CONS_INDEX              1
 511 +#define CONFIG_BAUDRATE                        115200
 512  #define CONFIG_SYS_BAUDRATE_TABLE      {9600, 19200, 38400, 57600, 115200}
 513
 514 -#define CONFIG_MMC_BASE                0x0
 515 -
 516  /***********************************************************
 517   * Command definition
 518   ***********************************************************/
 519 @@ -116,11 +134,13 @@
 520
 521  #define CONFIG_BOOTDELAY       3
 522
 523 +#define CONFIG_PRIME   "FEC0"
 524 +
 525  #define CONFIG_LOADADDR                0x90800000      /* loadaddr env var */
 526
 527  #define        CONFIG_EXTRA_ENV_SETTINGS                                       \
 528                 "netdev=eth0\0"                                         \
 529 -               "ethprime=smc911x\0"                                    \
 530 +               "ethprime=FEC0\0"                                       \
 531                 "uboot_addr=0xa0000000\0"                               \
 532                 "uboot=u-boot.bin\0"                    \
 533                 "kernel=uImage\0"                               \
 534 @@ -138,9 +158,11 @@
 535                         "setenv filesize; saveenv\0"
 536
 537  /*Support LAN9217*/
 538 +/*
 539  #define CONFIG_DRIVER_SMC911X  1
 540  #define CONFIG_DRIVER_SMC911X_16_BIT 1
 541  #define CONFIG_DRIVER_SMC911X_BASE_VARIABLE mx51_io_base_addr
 542 +*/
 543
 544  /*
 545   * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
 546 @@ -158,7 +180,8 @@
 547   * Miscellaneous configurable options
 548   */
 549  #define CONFIG_SYS_LONGHELP            /* undef to save memory */
 550 -#define CONFIG_SYS_PROMPT              "=> "
 551 +#define CONFIG_SYS_PROMPT              "BBG U-Boot > "
 552 +#define CONFIG_AUTO_COMPLETE
 553  #define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size */
 554  /* Print Buffer Size */
 555  #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 556 diff --git a/net/eth.c b/net/eth.c
 557 index bb8b6e4..67f6646 100644
 558 --- a/net/eth.c
 559 +++ b/net/eth.c
 560 @@ -201,8 +201,13 @@ int eth_initialize(bd_t *bis)
 561  #endif
 562         /* Try board-specific initialization first.  If it fails or isn't
 563          * present, try the cpu-specific initialization */
 564 +#ifdef CONFIG_ETH_PRIME
 565 +       board_eth_init(bis);
 566 +       cpu_eth_init(bis);
 567 +#else
 568         if (board_eth_init(bis) < 0)
 569                 cpu_eth_init(bis);
 570 +#endif
 571
 572  #if defined(CONFIG_DB64360) || defined(CONFIG_CPCI750)
 573         mv6436x_eth_initialize(bis);
 574 --
 575 1.5.4.4
 576