patches/0026-ENGR00114178-Support-MMC-SD-boot-and-enable-dhcp-in.patch

   1 From abf0610e5250ed69cc542e19f19c8a6812f4914e Mon Sep 17 00:00:00 2001
   2 From: Sammy <r62914@freescale.com>
   3 Date: Mon, 13 Jul 2009 15:05:16 +0800
   4 Subject: [PATCH] ENGR00114178 Support MMC/SD boot and enable dhcp in uboot on MX25
   5
   6 1. Support MMC/SD boot in uboot, however, it is disabled default and
   7  user needs to enable manually by changing mx25_3stack.h;
   8 2. Enable dhcp for network.
   9
  10 Signed-off-by: Sammy He <r62914@freescale.com>
  11 ---
  12  board/freescale/mx25_3stack/mx25_3stack.c |   85 +++++++++++
  13  include/asm-arm/arch-mx25/mmc.h           |   16 ++
  14  include/asm-arm/arch-mx25/sdhc.h          |  218 +++++++++++++++++++++++++++++
  15  include/configs/mx25_3stack.h             |   38 +++++-
  16  4 files changed, 355 insertions(+), 2 deletions(-)
  17
  18 diff --git a/board/freescale/mx25_3stack/mx25_3stack.c b/board/freescale/mx25_3stack/mx25_3stack.c
  19 index 22559b6..b33eaa1 100644
  20 --- a/board/freescale/mx25_3stack/mx25_3stack.c
  21 +++ b/board/freescale/mx25_3stack/mx25_3stack.c
  22 @@ -35,6 +35,7 @@
  23  DECLARE_GLOBAL_DATA_PTR;
  24
  25  static u32 system_rev;
  26 +volatile u32 *esdhc_base_pointer;
  27
  28  u32 get_board_rev(void)
  29  {
  30 @@ -53,6 +54,11 @@ static inline void setup_soc_rev(void)
  31         system_rev = 0x25000 + (reg & 0xFF);
  32  }
  33
  34 +inline int is_soc_rev(int rev)
  35 +{
  36 +       return (system_rev & 0xFF) - rev;
  37 +}
  38 +
  39  int dram_init(void)
  40  {
  41         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  42 @@ -61,6 +67,85 @@ int dram_init(void)
  43         return 0;
  44  }
  45
  46 +#ifdef CONFIG_FSL_MMC
  47 +
  48 +int sdhc_init(void)
  49 +{
  50 +       u32 interface_esdhc = 0, val = 0;
  51 +
  52 +       interface_esdhc = (readl(CCM_RCSR) & (0x00300000)) >> 20;
  53 +
  54 +       switch (interface_esdhc) {
  55 +       case 0:
  56 +               esdhc_base_pointer = (volatile u32 *)MMC_SDHC1_BASE;
  57 +               /* Pins */
  58 +               writel(0x10, IOMUXC_BASE + 0x190);      /* SD1_CMD */
  59 +               writel(0x10, IOMUXC_BASE + 0x194);      /* SD1_CLK */
  60 +               writel(0x00, IOMUXC_BASE + 0x198);      /* SD1_DATA0 */
  61 +               writel(0x00, IOMUXC_BASE + 0x19c);      /* SD1_DATA1 */
  62 +               writel(0x00, IOMUXC_BASE + 0x1a0);      /* SD1_DATA2 */
  63 +               writel(0x00, IOMUXC_BASE + 0x1a4);      /* SD1_DATA3 */
  64 +               writel(0x06, IOMUXC_BASE + 0x094);      /* D12 (SD1_DATA4) */
  65 +               writel(0x06, IOMUXC_BASE + 0x090);      /* D13 (SD1_DATA5) */
  66 +               writel(0x06, IOMUXC_BASE + 0x08c);      /* D14 (SD1_DATA6) */
  67 +               writel(0x06, IOMUXC_BASE + 0x088);      /* D15 (SD1_DATA7) */
  68 +               writel(0x05, IOMUXC_BASE + 0x010);      /* A14 (SD1_WP) */
  69 +               writel(0x05, IOMUXC_BASE + 0x014);      /* A15 (SD1_DET) */
  70 +
  71 +               /* Pads */
  72 +               writel(0xD1, IOMUXC_BASE + 0x388);      /* SD1_CMD */
  73 +               writel(0xD1, IOMUXC_BASE + 0x38c);      /* SD1_CLK */
  74 +               writel(0xD1, IOMUXC_BASE + 0x390);      /* SD1_DATA0 */
  75 +               writel(0xD1, IOMUXC_BASE + 0x394);      /* SD1_DATA1 */
  76 +               writel(0xD1, IOMUXC_BASE + 0x398);      /* SD1_DATA2 */
  77 +               writel(0xD1, IOMUXC_BASE + 0x39c);      /* SD1_DATA3 */
  78 +               writel(0xD1, IOMUXC_BASE + 0x28c);      /* D12 (SD1_DATA4) */
  79 +               writel(0xD1, IOMUXC_BASE + 0x288);      /* D13 (SD1_DATA5) */
  80 +               writel(0xD1, IOMUXC_BASE + 0x284);      /* D14 (SD1_DATA6) */
  81 +               writel(0xD1, IOMUXC_BASE + 0x280);      /* D15 (SD1_DATA7) */
  82 +               writel(0xD1, IOMUXC_BASE + 0x230);      /* A14 (SD1_WP) */
  83 +               writel(0xD1, IOMUXC_BASE + 0x234);      /* A15 (SD1_DET) */
  84 +
  85 +               /*
  86 +                * Set write protect and card detect gpio as inputs
  87 +                * A14 (SD1_WP) and A15 (SD1_DET)
  88 +                */
  89 +               val = ~(3 << 0) & readl(GPIO1_BASE + GPIO_GDIR);
  90 +               writel(val, GPIO1_BASE + GPIO_GDIR);
  91 +               break;
  92 +       case 1:
  93 +               esdhc_base_pointer = (volatile u32 *)MMC_SDHC2_BASE;
  94 +               /* Pins */
  95 +               writel(0x16, IOMUXC_BASE + 0x0e8);      /* LD8 (SD1_CMD) */
  96 +               writel(0x16, IOMUXC_BASE + 0x0ec);      /* LD9 (SD1_CLK) */
  97 +               writel(0x06, IOMUXC_BASE + 0x0f0);      /* LD10 (SD1_DATA0) */
  98 +               writel(0x06, IOMUXC_BASE + 0x0f4);      /* LD11 (SD1_DATA1) */
  99 +               writel(0x06, IOMUXC_BASE + 0x0f8);      /* LD12 (SD1_DATA2) */
 100 +               writel(0x06, IOMUXC_BASE + 0x0fc);      /* LD13 (SD1_DATA3) */
 101 +               writel(0x02, IOMUXC_BASE + 0x120);      /* CSI_D2 (SD1_DATA4) */
 102 +               writel(0x02, IOMUXC_BASE + 0x124);      /* CSI_D3 (SD1_DATA5) */
 103 +               writel(0x02, IOMUXC_BASE + 0x128);      /* CSI_D4 (SD1_DATA6) */
 104 +               writel(0x02, IOMUXC_BASE + 0x12c);      /* CSI_D5 (SD1_DATA7) */
 105 +
 106 +               /* Pads */
 107 +               writel(0xD1, IOMUXC_BASE + 0x2e0);      /* LD8 (SD1_CMD) */
 108 +               writel(0xD1, IOMUXC_BASE + 0x2e4);      /* LD9 (SD1_CLK) */
 109 +               writel(0xD1, IOMUXC_BASE + 0x2e8);      /* LD10 (SD1_DATA0) */
 110 +               writel(0xD1, IOMUXC_BASE + 0x2ec);      /* LD11 (SD1_DATA1) */
 111 +               writel(0xD1, IOMUXC_BASE + 0x2f0);      /* LD12 (SD1_DATA2) */
 112 +               writel(0xD1, IOMUXC_BASE + 0x2f4);      /* LD13 (SD1_DATA3) */
 113 +               writel(0xD1, IOMUXC_BASE + 0x318);      /* CSI_D2 (SD1_DATA4) */
 114 +               writel(0xD1, IOMUXC_BASE + 0x31c);      /* CSI_D3 (SD1_DATA5) */
 115 +               writel(0xD1, IOMUXC_BASE + 0x320);      /* CSI_D4 (SD1_DATA6) */
 116 +               writel(0xD1, IOMUXC_BASE + 0x324);      /* CSI_D5 (SD1_DATA7) */
 117 +               break;
 118 +       default:
 119 +               break;
 120 +       }
 121 +       return 0;
 122 +}
 123 +#endif
 124 +
 125  int board_init(void)
 126  {
 127         int pad;
 128 diff --git a/include/asm-arm/arch-mx25/mmc.h b/include/asm-arm/arch-mx25/mmc.h
 129 new file mode 100644
 130 index 0000000..5f12934
 131 --- /dev/null
 132 +++ b/include/asm-arm/arch-mx25/mmc.h
 133 @@ -0,0 +1,16 @@
 134 +/*
 135 + *  (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
 136 + *
 137 + *  linux/drivers/mmc/mmc.h
 138 + *
 139 + *  Author: Vladimir Shebordaev, Igor Oblakov
 140 + *  Copyright:  MontaVista Software Inc.
 141 + *
 142 + *  This program is free software; you can redistribute it and/or modify
 143 + *  it under the terms of the GNU General Public License version 2 as
 144 + *  published by the Free Software Foundation.
 145 + */
 146 +#ifndef __MMC_MX25_3STACK_H__
 147 +#define __MMC_MX25_3STACK_H__
 148 +
 149 +#endif /* __MMC_MX51_3STACK_H__ */
 150 diff --git a/include/asm-arm/arch-mx25/sdhc.h b/include/asm-arm/arch-mx25/sdhc.h
 151 new file mode 100644
 152 index 0000000..5514ad4
 153 --- /dev/null
 154 +++ b/include/asm-arm/arch-mx25/sdhc.h
 155 @@ -0,0 +1,218 @@
 156 +/*
 157 + * Copyright 2008-2009 Freescale Semiconductor, Inc.
 158 + *
 159 + * See file CREDITS for list of people who contributed to this
 160 + * project.
 161 + *
 162 + * This program is free software; you can redistribute it and/or
 163 + * modify it under the terms of the GNU General Public License as
 164 + * published by the Free Software Foundation; either version 2 of
 165 + * the License, or (at your option) any later version.
 166 + *
 167 + * This program is distributed in the hope that it will be useful,
 168 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 169 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 170 + * GNU General Public License for more details.
 171 + *
 172 + * You should have received a copy of the GNU General Public License
 173 + * along with this program; if not, write to the Free Software
 174 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 175 + * MA 02111-1307 USA
 176 + */
 177 +
 178 +#ifndef SDHC_H
 179 +#define SDHC_H
 180 +
 181 +#include <linux/types.h>
 182 +
 183 +#define ESDHC_SOFTWARE_RESET_DATA ((u32)0x04000000)
 184 +#define ESDHC_SOFTWARE_RESET_CMD  ((u32)0x02000000)
 185 +#define ESDHC_SOFTWARE_RESET      ((u32)0x01000000)
 186 +#define ESDHC_CMD_INHIBIT       0x00000003
 187 +#define ESDHC_SYSCTL_INITA        ((u32)0x08000000)
 188 +#define ESDHC_LITTLE_ENDIAN_MODE  ((u32)0x00000020)
 189 +#define ESDHC_HW_BIG_ENDIAN_MODE  ((u32)0x00000010)
 190 +#define ESDHC_BIG_ENDIAN_MODE     ((u32)0x00000000)
 191 +#define ESDHC_ONE_BIT_SUPPORT     ((u32)0x00000000)
 192 +#define ESDHC_FOUR_BIT_SUPPORT    ((u32)0x00000002)
 193 +#define ESDHC_EIGHT_BIT_SUPPORT   ((u32)0x00000004)
 194 +#define ESDHC_CLOCK_ENABLE             0x00000007
 195 +#define ESDHC_FREQ_MASK 0xffff0007
 196 +#define ESDHC_SYSCTL_FREQ_MASK    ((u32)0x000FFFF0)
 197 +#define ESDHC_SYSCTL_IDENT_FREQ_TO1   ((u32)0x0000800e)
 198 +#define ESDHC_SYSCTL_OPERT_FREQ_TO1   ((u32)0x00000200)
 199 +#define ESDHC_SYSCTL_IDENT_FREQ_TO2   ((u32)0x00002040)
 200 +#define ESDHC_SYSCTL_OPERT_FREQ_TO2   ((u32)0x00000050)
 201 +#define ESDHC_INTERRUPT_ENABLE    ((u32)0x007f0133)
 202 +#define ESDHC_CLEAR_INTERRUPT     ((u32)0x117f01ff)
 203 +#define ESDHC_SYSCTL_DTOCV_VAL    ((u32)0x000E0000)
 204 +#define ESDHC_IRQSTATEN_DTOESEN   ((u32)0x00100000)
 205 +#define ESDHC_ENDIAN_MODE_MASK    ((u32)0x00000030)
 206 +#define ESDHC_SYSCTRL_RSTC        ((u32)0x02000000)
 207 +#define ESDHC_SYSCTRL_RSTD        ((u32)0x04000000)
 208 +#define ESDHC_CONFIG_BLOCK 0x00010200
 209 +#define ESDHC_OPER_TIMEOUT (96 * 100)
 210 +#define ESDHC_ACMD41_TIMEOUT      (32000)
 211 +#define ESDHC_CMD1_TIMEOUT        (32000)
 212 +#define ESDHC_BLOCK_SHIFT         (16)
 213 +#define ESDHC_CARD_INIT_TIMEOUT   (64)
 214 +
 215 +#define ESDHC_SYSCTL_SDCLKEN_MASK     ((u32)0x00000008)
 216 +#define ESDHC_PRSSTAT_SDSTB_BIT       ((u32)0x00000008)
 217 +#define ESDHC_SYSCTL_INPUT_CLOCK_MASK ((u32)0x00000007)
 218 +
 219 +#define ESDHC_BUS_WIDTH_MASK                    ((u32)0x00000006)
 220 +#define ESDHC_DATA_TRANSFER_SHIFT               (4)
 221 +#define ESDHC_RESPONSE_FORMAT_SHIFT             (16)
 222 +#define ESDHC_DATA_PRESENT_SHIFT                (21)
 223 +#define ESDHC_CRC_CHECK_SHIFT                   (19)
 224 +#define ESDHC_CMD_INDEX_CHECK_SHIFT             (20)
 225 +#define ESDHC_CMD_INDEX_SHIFT                   (24)
 226 +#define ESDHC_BLOCK_COUNT_ENABLE_SHIFT          (1)
 227 +#define ESDHC_MULTI_SINGLE_BLOCK_SELECT_SHIFT   (5)
 228 +#define BLK_LEN                                        (512)
 229 +#define ESDHC_READ_WATER_MARK_LEVEL_BL_4       ((u32)0x00000001)
 230 +#define ESDHC_READ_WATER_MARK_LEVEL_BL_8       ((u32)0x00000002)
 231 +#define ESDHC_READ_WATER_MARK_LEVEL_BL_16      ((u32)0x00000004)
 232 +#define ESDHC_READ_WATER_MARK_LEVEL_BL_64      ((u32)0x00000010)
 233 +#define ESDHC_READ_WATER_MARK_LEVEL_BL_512     ((u32)0x00000080)
 234 +
 235 +#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_4      ((u32)0x00010000)
 236 +#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_8      ((u32)0x00020000)
 237 +#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_16     ((u32)0x00040000)
 238 +#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_64     ((u32)0x00100000)
 239 +#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_512    ((u32)0x00800000)
 240 +
 241 +#define WRITE_READ_WATER_MARK_LEVEL 0x00800080
 242 +
 243 +/* Present State register bit masks */
 244 +#define ESDHC_PRESENT_STATE_CIHB    ((u32)0x00000001)
 245 +#define ESDHC_PRESENT_STATE_CDIHB   ((u32)0x00000002)
 246 +#define ONE                         (1)
 247 +#define ESDHC_FIFO_SIZE             (128)
 248 +
 249 +#define ESDHC_STATUS_END_CMD_RESP_MSK         ((u32)0x00000001)
 250 +#define ESDHC_STATUS_END_CMD_RESP_TIME_MSK    ((u32)0x000F0001)
 251 +#define ESDHC_STATUS_TIME_OUT_RESP_MSK        ((u32)0x00010000)
 252 +#define ESDHC_STATUS_RESP_CRC_ERR_MSK         ((u32)0x00020000)
 253 +#define ESDHC_STATUS_RESP_CMD_INDEX_ERR_MSK   ((u32)0x00080000)
 254 +#define ESDHC_STATUS_BUF_READ_RDY_MSK         ((u32)0x00000020)
 255 +#define ESDHC_STATUS_BUF_WRITE_RDY_MSK        ((u32)0x00000010)
 256 +#define ESDHC_STATUS_TRANSFER_COMPLETE_MSK    ((u32)0x00000002)
 257 +#define ESDHC_STATUS_DATA_RW_MSK              ((u32)0x00700002)
 258 +#define ESDHC_STATUS_TRANSFER_COMPLETE_MSK    ((u32)0x00000002)
 259 +#define ESDHC_STATUS_TIME_OUT_READ_MASK       ((u32)0x00100000)
 260 +#define ESDHC_STATUS_READ_CRC_ERR_MSK         ((u32)0x00200000)
 261 +#define ESDHC_STATUS_RESP_CMD_END_BIT_ERR_MSK ((u32)0x00040000)
 262 +#define ESDHC_STATUS_RW_DATA_END_BIT_ERR_MSK  ((u32)0x00400000)
 263 +
 264 +#define ESDHC_STATUS_TIME_OUT_READ  (3200)
 265 +#define ESDHC_READ_DATA_TIME_OUT    (3200)
 266 +#define ESDHC_WRITE_DATA_TIME_OUT   (8000)
 267 +
 268 +#define ESDHC_CONFIG_BLOCK_512      ((u32)0x00000200)
 269 +#define ESDHC_CONFIG_BLOCK_64       ((u32)0x00000040)
 270 +#define ESDHC_CONFIG_BLOCK_8        ((u32)0x00000008)
 271 +#define ESDHC_CONFIG_BLOCK_4        ((u32)0x00000004)
 272 +
 273 +#define ESDHC_MAX_BLOCK_COUNT       ((u32)0x0000ffff)
 274 +
 275 +typedef enum {
 276 +       ESDHC1,
 277 +       ESDHC2,
 278 +       ESDHC3
 279 +} esdhc_num_t;
 280 +
 281 +typedef enum {
 282 +       WRITE,
 283 +       READ,
 284 +} xfer_type_t;
 285 +
 286 +typedef enum {
 287 +       RESPONSE_NONE,
 288 +       RESPONSE_136,
 289 +       RESPONSE_48,
 290 +       RESPONSE_48_CHECK_BUSY
 291 +} response_format_t;
 292 +
 293 +
 294 +typedef enum {
 295 +       DATA_PRESENT_NONE,
 296 +       DATA_PRESENT
 297 +} data_present_select;
 298 +
 299 +typedef enum {
 300 +       DISABLE,
 301 +       ENABLE
 302 +} crc_check_enable, cmdindex_check_enable, block_count_enable;
 303 +
 304 +typedef enum {
 305 +       SINGLE,
 306 +       MULTIPLE
 307 +} multi_single_block_select;
 308 +
 309 +typedef struct {
 310 +       u32 command;
 311 +       u32 arg;
 312 +       xfer_type_t data_transfer;
 313 +       response_format_t response_format;
 314 +       data_present_select data_present;
 315 +       crc_check_enable crc_check;
 316 +       cmdindex_check_enable cmdindex_check;
 317 +       block_count_enable block_count_enable_check;
 318 +       multi_single_block_select multi_single_block;
 319 +} esdhc_cmd_t;
 320 +
 321 +typedef struct {
 322 +       response_format_t format;
 323 +       u32 cmd_rsp0;
 324 +       u32 cmd_rsp1;
 325 +       u32 cmd_rsp2;
 326 +       u32 cmd_rsp3;
 327 +} esdhc_resp_t;
 328 +
 329 +typedef enum {
 330 +       BIG_ENDIAN,
 331 +       HALF_WORD_BIG_ENDIAN,
 332 +       LITTLE_ENDIAN
 333 +} endian_mode_t;
 334 +
 335 +typedef enum {
 336 +       OPERATING_FREQ = 20000,   /* in kHz */
 337 +       IDENTIFICATION_FREQ = 400   /* in kHz */
 338 +} sdhc_freq_t;
 339 +
 340 +enum esdhc_data_status {
 341 +       ESDHC_DATA_ERR = 3,
 342 +       ESDHC_DATA_OK = 4
 343 +};
 344 +
 345 +enum esdhc_int_cntr_val {
 346 +       ESDHC_INT_CNTR_END_CD_RESP = 0x4,
 347 +       ESDHC_INT_CNTR_BUF_WR_RDY = 0x8
 348 +};
 349 +
 350 +enum esdhc_reset_status {
 351 +       ESDHC_WRONG_RESET = 0,
 352 +       ESDHC_CORRECT_RESET = 1
 353 +};
 354 +
 355 +typedef enum {
 356 +       WEAK = 0,
 357 +       STRONG = 1
 358 +} esdhc_pullup_t;
 359 +
 360 +extern u32 interface_reset(void);
 361 +extern void interface_configure_clock(sdhc_freq_t);
 362 +extern void interface_read_response(esdhc_resp_t *);
 363 +extern u32 interface_send_cmd_wait_resp(esdhc_cmd_t *);
 364 +extern u32 interface_data_read(u32 *, u32);
 365 +extern void interface_config_block_info(u32, u32, u32);
 366 +extern u32 interface_data_write(u32 *, u32);
 367 +extern void interface_clear_interrupt(void);
 368 +extern void interface_initialization_active(void);
 369 +extern void esdhc_set_cmd_pullup(esdhc_pullup_t pull_up);
 370 +extern void esdhc_soft_reset(u32 mask);
 371 +extern u32 interface_set_bus_width(u32 bus_width);
 372 +/*================================================================================================*/
 373 +#endif  /* ESDHC_H */
 374 diff --git a/include/configs/mx25_3stack.h b/include/configs/mx25_3stack.h
 375 index 05b3500..5e343ea 100644
 376 --- a/include/configs/mx25_3stack.h
 377 +++ b/include/configs/mx25_3stack.h
 378 @@ -97,6 +97,17 @@
 379  /* #define CONFIG_CMD_DATE */
 380  #define CONFIG_CMD_NAND
 381
 382 +/*
 383 + * MMC Configs
 384 + * */
 385 +/*
 386 +#define CONFIG_FSL_MMC
 387 +#define CONFIG_MMC
 388 +#define CONFIG_CMD_MMC
 389 +#define CONFIG_DOS_PARTITION
 390 +#define CONFIG_CMD_FAT
 391 +#define CONFIG_MMC_BASE       0x0  */
 392 +
 393  /* Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
 394   * that CONFIG_NO_FLASH is undefined).
 395   */
 396 @@ -122,6 +133,8 @@
 397  #define CONFIG_DRIVER_SMC911X_BASE CS5_BASE*/
 398
 399  /*#define CONFIG_HAS_ETH1*/
 400 +#define CONFIG_CMD_NET
 401 +#define CONFIG_CMD_DHCP
 402  #define CONFIG_NET_MULTI       1
 403  #define CONFIG_MXC_FEC
 404  #define CONFIG_MII
 405 @@ -174,12 +187,33 @@
 406  #else
 407  #define PHYS_SDRAM_1_SIZE       (64 * 1024 * 1024)
 408  #endif
 409 +
 410 +/* Monitor at beginning of flash */
 411 +#if defined(CONFIG_FSL_SF)
 412 +       #define CONFIG_FSL_ENV_IN_SF
 413 +#elif defined(CONFIG_FSL_MMC)
 414 +       #define CONFIG_FSL_ENV_IN_MMC
 415 +#elif defined(CONFIG_CMD_NAND)
 416 +       #define CONFIG_FSL_ENV_IN_NAND
 417 +#endif
 418 +
 419  /*-----------------------------------------------------------------------
 420   * FLASH and environment organization
 421   */
 422 +#if defined(CONFIG_FSL_ENV_IN_NAND)
 423 +       #define CONFIG_ENV_IS_IN_NAND 1
 424 +       #define CONFIG_ENV_OFFSET       0x80000
 425 +#elif defined(CONFIG_FSL_ENV_IN_MMC)
 426 +       #define CONFIG_ENV_IS_IN_MMC    1
 427 +       #define CONFIG_ENV_OFFSET       0x100000
 428 +#elif defined(CONFIG_FSL_ENV_IN_SF)
 429 +       #define CONFIG_ENV_IS_IN_SPI_FLASH      1
 430 +       #define CONFIG_ENV_SPI_CS               1
 431 +       #define CONFIG_ENV_OFFSET               0x100000
 432 +#else
 433 +       #define CONFIG_ENV_IS_NOWHERE   1
 434 +#endif
 435
 436 -#define        CONFIG_ENV_IS_IN_NAND   1
 437 -#define CONFIG_ENV_OFFSET              0x80000 /* 2nd block */
 438  #define CONFIG_ENV_SECT_SIZE   (256 * 1024)
 439  #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 440
 441 --
 442 1.5.4.4
 443