patches/0054-ENGR00118579-Enable-MMU.patch

   1 From 3f86cf9693f8b98c44999e81d4067943c634b421 Mon Sep 17 00:00:00 2001
   2 From: Fred Fan <r01011@freescale.com>
   3 Date: Thu, 19 Nov 2009 16:43:08 +0800
   4 Subject: [PATCH] ENGR00118579 Enable MMU
   5
   6 To enable MMU, it is porting from redboot.
   7 Enable MMU and enable I/D cache.
   8
   9 Signed-off-by:Fred Fan <r01011@freescale.com>
  10 ---
  11  board/freescale/mx35_3stack/mx35_3stack.c |   66 ++++++++++++++
  12  cpu/arm1136/mx35/generic.c                |    9 ++
  13  cpu/arm1136/start.S                       |    4 +-
  14  include/asm-arm/arch                      |    1 +
  15  include/asm-arm/arch-mx35/mmu.h           |  135 +++++++++++++++++++++++++++++
  16  include/asm-arm/mmu.h                     |   79 +++++++++++++++++
  17  include/asm-arm/proc                      |    1 +
  18  include/configs/mx35_3stack.h             |    2 +
  19  8 files changed, 296 insertions(+), 1 deletions(-)
  20
  21 diff --git a/board/freescale/mx35_3stack/mx35_3stack.c b/board/freescale/mx35_3stack/mx35_3stack.c
  22 index bd6585b..9eea6ad 100644
  23 --- a/board/freescale/mx35_3stack/mx35_3stack.c
  24 +++ b/board/freescale/mx35_3stack/mx35_3stack.c
  25 @@ -36,6 +36,10 @@
  26  #include <fsl_esdhc.h>
  27  #endif
  28
  29 +#ifdef CONFIG_ARCH_MMU
  30 +#include <asm/mmu.h>
  31 +#include <asm/arch/mmu.h>
  32 +#endif
  33
  34  DECLARE_GLOBAL_DATA_PTR;
  35
  36 @@ -68,6 +72,68 @@ int is_soc_rev(int rev)
  37         return (system_rev & 0xFF) - rev;
  38  }
  39
  40 +#ifdef CONFIG_ARCH_MMU
  41 +void board_mmu_init(void)
  42 +{
  43 +       unsigned long ttb_base = PHYS_SDRAM_1 + 0x40000;
  44 +       unsigned long i;
  45 +
  46 +       /*
  47 +        * Set the TTB register
  48 +        */
  49 +       asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
  50 +
  51 +       /*
  52 +        * Set the Domain Access Control Register
  53 +        */
  54 +       i = ARM_ACCESS_DACR_DEFAULT;
  55 +       asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
  56 +
  57 +       /*
  58 +        * First clear all TT entries - ie Set them to Faulting
  59 +        */
  60 +       memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
  61 +       /* Actual   Virtual  Size   Attributes          Function */
  62 +       /* Base     Base     MB     cached? buffered?  access permissions */
  63 +       /* xxx00000 xxx00000 */
  64 +       X_ARM_MMU_SECTION(0x000, 0xF00, 0x1,
  65 +                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  66 +                         ARM_ACCESS_PERM_RW_RW); /* ROM */
  67 +       X_ARM_MMU_SECTION(0x100, 0x100, 0x1,
  68 +                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  69 +                         ARM_ACCESS_PERM_RW_RW); /* iRAM */
  70 +       X_ARM_MMU_SECTION(0x300, 0x300, 0x1,
  71 +                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  72 +                         ARM_ACCESS_PERM_RW_RW); /* L2CC */
  73 +       /* Internal Regsisters upto SDRAM*/
  74 +       X_ARM_MMU_SECTION(0x400, 0x400, 0x400,
  75 +                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  76 +                         ARM_ACCESS_PERM_RW_RW);
  77 +       X_ARM_MMU_SECTION(0x800, 0x000, 0x80,
  78 +                         ARM_CACHEABLE, ARM_BUFFERABLE,
  79 +                         ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
  80 +       X_ARM_MMU_SECTION(0x800, 0x800, 0x80,
  81 +                         ARM_CACHEABLE, ARM_BUFFERABLE,
  82 +                         ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
  83 +       X_ARM_MMU_SECTION(0x800, 0x880, 0x80,
  84 +                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  85 +                         ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
  86 +       X_ARM_MMU_SECTION(0x900, 0x900, 0x80,
  87 +                         ARM_CACHEABLE, ARM_BUFFERABLE,
  88 +                         ARM_ACCESS_PERM_RW_RW); /* SDRAM 1:128M*/
  89 +       X_ARM_MMU_SECTION(0xA00, 0xA00, 0x40,
  90 +                         ARM_CACHEABLE, ARM_BUFFERABLE,
  91 +                         ARM_ACCESS_PERM_RW_RW); /* Flash */
  92 +       X_ARM_MMU_SECTION(0xB00, 0xB00, 0x20,
  93 +                         ARM_CACHEABLE, ARM_BUFFERABLE,
  94 +                         ARM_ACCESS_PERM_RW_RW); /* PSRAM */
  95 +       /* ESDCTL, WEIM, M3IF, EMI, NFC, External I/O */
  96 +       X_ARM_MMU_SECTION(0xB20, 0xB20, 0x1E0,
  97 +                         ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  98 +                         ARM_ACCESS_PERM_RW_RW);
  99 +}
 100 +#endif
 101 +
 102  int dram_init(void)
 103  {
 104         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 105 diff --git a/cpu/arm1136/mx35/generic.c b/cpu/arm1136/mx35/generic.c
 106 index 31bcbec..fbe9084 100644
 107 --- a/cpu/arm1136/mx35/generic.c
 108 +++ b/cpu/arm1136/mx35/generic.c
 109 @@ -372,3 +372,12 @@ int cpu_eth_init(bd_t *bis)
 110  #endif
 111         return rc;
 112  }
 113 +
 114 +#if defined(CONFIG_ARCH_CPU_INIT)
 115 +int arch_cpu_init(void)
 116 +{
 117 +       icache_enable();
 118 +       dcache_enable();
 119 +       return 0;
 120 +}
 121 +#endif
 122 diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S
 123 index b1d7087..2da16e7 100644
 124 --- a/cpu/arm1136/start.S
 125 +++ b/cpu/arm1136/start.S
 126 @@ -251,7 +251,9 @@ clbss_l:str r2, [r0]                /* clear loop...                    */
 127         cmp     r0, r1
 128         bne     clbss_l
 129  #endif
 130 -
 131 +#ifdef CONFIG_ARCH_MMU
 132 +       bl board_mmu_init
 133 +#endif
 134         ldr     pc, _start_armboot
 135
 136  #ifdef CONFIG_NAND_SPL
 137 diff --git a/include/asm-arm/arch b/include/asm-arm/arch
 138 new file mode 120000
 139 index 0000000..cd1d867
 140 --- /dev/null
 141 +++ b/include/asm-arm/arch
 142 @@ -0,0 +1 @@
 143 +arch-mx35
 144 \ No newline at end of file
 145 diff --git a/include/asm-arm/arch-mx35/mmu.h b/include/asm-arm/arch-mx35/mmu.h
 146 new file mode 100644
 147 index 0000000..a701c72
 148 --- /dev/null
 149 +++ b/include/asm-arm/arch-mx35/mmu.h
 150 @@ -0,0 +1,135 @@
 151 +/*
 152 + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
 153 + */
 154 +
 155 +/*
 156 + * The code contained herein is licensed under the GNU General Public
 157 + * License. You may obtain a copy of the GNU General Public License
 158 + * Version 2 or later at the following locations:
 159 + *
 160 + * http://www.opensource.org/licenses/gpl-license.html
 161 + * http://www.gnu.org/copyleft/gpl.html
 162 + */
 163 +
 164 +#ifndef __ARM_ARCH_MMU_H
 165 +#define __ARM_ARCH_MMU_H
 166 +
 167 +/*
 168 + * Translation Table Base Bit Masks
 169 + */
 170 +#define ARM_TRANSLATION_TABLE_MASK               0xFFFFC000
 171 +
 172 +/*
 173 + * Domain Access Control Bit Masks
 174 + */
 175 +#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)    (0x0 << (domain_num)*2)
 176 +#define ARM_ACCESS_TYPE_CLIENT(domain_num)       (0x1 << (domain_num)*2)
 177 +#define ARM_ACCESS_TYPE_MANAGER(domain_num)      (0x3 << (domain_num)*2)
 178 +
 179 +struct ARM_MMU_FIRST_LEVEL_FAULT {
 180 +       unsigned int id:2;
 181 +       unsigned int sbz:30;
 182 +};
 183 +
 184 +#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
 185 +
 186 +struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
 187 +       unsigned int id:2;
 188 +       unsigned int imp:2;
 189 +       unsigned int domain:4;
 190 +       unsigned int sbz:1;
 191 +       unsigned int base_address:23;
 192 +};
 193 +
 194 +#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
 195 +
 196 +struct ARM_MMU_FIRST_LEVEL_SECTION {
 197 +       unsigned int id:2;
 198 +       unsigned int b:1;
 199 +       unsigned int c:1;
 200 +       unsigned int imp:1;
 201 +       unsigned int domain:4;
 202 +       unsigned int sbz0:1;
 203 +       unsigned int ap:2;
 204 +       unsigned int sbz1:8;
 205 +       unsigned int base_address:12;
 206 +};
 207 +
 208 +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
 209 +
 210 +struct ARM_MMU_FIRST_LEVEL_RESERVED {
 211 +       unsigned int id:2;
 212 +       unsigned int sbz:30;
 213 +};
 214 +
 215 +#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
 216 +
 217 +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
 218 +       (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
 219 +
 220 +#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
 221 +
 222 +#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,           \
 223 +                       cacheable, bufferable, perm)                    \
 224 +       {                                                               \
 225 +       register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;             \
 226 +       desc.word = 0;                                                  \
 227 +       desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;               \
 228 +       desc.section.domain = 0;                                        \
 229 +       desc.section.c = (cacheable);                                   \
 230 +       desc.section.b = (bufferable);                                  \
 231 +       desc.section.ap = (perm);                                       \
 232 +       desc.section.base_address = (actual_base);                      \
 233 +       *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
 234 +                               = desc.word;                            \
 235 +       }
 236 +
 237 +#define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access)     \
 238 +       {                                                               \
 239 +               int i; int j = abase; int k = vbase;                    \
 240 +               for (i = size; i > 0 ; i--, j++, k++)                   \
 241 +                       ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
 242 +       }
 243 +
 244 +union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
 245 +       unsigned long word;
 246 +       struct ARM_MMU_FIRST_LEVEL_FAULT fault;
 247 +       struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
 248 +       struct ARM_MMU_FIRST_LEVEL_SECTION section;
 249 +       struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
 250 +};
 251 +
 252 +#define ARM_UNCACHEABLE                0
 253 +#define ARM_CACHEABLE          1
 254 +#define ARM_UNBUFFERABLE       0
 255 +#define ARM_BUFFERABLE         1
 256 +
 257 +#define ARM_ACCESS_PERM_NONE_NONE      0
 258 +#define ARM_ACCESS_PERM_RO_NONE                0
 259 +#define ARM_ACCESS_PERM_RO_RO          0
 260 +#define ARM_ACCESS_PERM_RW_NONE                1
 261 +#define ARM_ACCESS_PERM_RW_RO          2
 262 +#define ARM_ACCESS_PERM_RW_RW          3
 263 +
 264 +/*
 265 + * Initialization for the Domain Access Control Register
 266 + */
 267 +#define ARM_ACCESS_DACR_DEFAULT      ( \
 268 +       ARM_ACCESS_TYPE_MANAGER(0)    | \
 269 +       ARM_ACCESS_TYPE_NO_ACCESS(1)  | \
 270 +       ARM_ACCESS_TYPE_NO_ACCESS(2)  | \
 271 +       ARM_ACCESS_TYPE_NO_ACCESS(3)  | \
 272 +       ARM_ACCESS_TYPE_NO_ACCESS(4)  | \
 273 +       ARM_ACCESS_TYPE_NO_ACCESS(5)  | \
 274 +       ARM_ACCESS_TYPE_NO_ACCESS(6)  | \
 275 +       ARM_ACCESS_TYPE_NO_ACCESS(7)  | \
 276 +       ARM_ACCESS_TYPE_NO_ACCESS(8)  | \
 277 +       ARM_ACCESS_TYPE_NO_ACCESS(9)  | \
 278 +       ARM_ACCESS_TYPE_NO_ACCESS(10) | \
 279 +       ARM_ACCESS_TYPE_NO_ACCESS(11) | \
 280 +       ARM_ACCESS_TYPE_NO_ACCESS(12) | \
 281 +       ARM_ACCESS_TYPE_NO_ACCESS(13) | \
 282 +       ARM_ACCESS_TYPE_NO_ACCESS(14) | \
 283 +       ARM_ACCESS_TYPE_NO_ACCESS(15))
 284 +
 285 +#endif
 286 diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h
 287 new file mode 100644
 288 index 0000000..668dfc9
 289 --- /dev/null
 290 +++ b/include/asm-arm/mmu.h
 291 @@ -0,0 +1,79 @@
 292 +/*
 293 + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
 294 + */
 295 +
 296 +/*
 297 + * The code contained herein is licensed under the GNU General Public
 298 + * License. You may obtain a copy of the GNU General Public License
 299 + * Version 2 or later at the following locations:
 300 + *
 301 + * http://www.opensource.org/licenses/gpl-license.html
 302 + * http://www.gnu.org/copyleft/gpl.html
 303 + */
 304 +
 305 +#ifndef __ASM_MMU_H
 306 +#define __ASM_MMU_H
 307 +
 308 +
 309 +#define MMU_L1_TYPE         0x03  /* Descriptor type */
 310 +#define MMU_L1_TYPE_Fault   0x00  /* Invalid */
 311 +#define MMU_L1_TYPE_Page    0x11  /* Individual page mapping */
 312 +#define MMU_L1_TYPE_Section 0x12  /* Mapping for 1M segment */
 313 +
 314 +#define MMU_L2_TYPE         0x03  /* Descriptor type */
 315 +#define MMU_L2_TYPE_Fault   0x00  /* Invalid data */
 316 +#define MMU_L2_TYPE_Large   0x01  /* Large page (64K) */
 317 +#define MMU_L2_TYPE_Small   0x02  /* Small page (4K) */
 318 +
 319 +#define MMU_Bufferable      0x04  /* Data can use write-buffer */
 320 +#define MMU_Cacheable       0x08  /* Data can use cache */
 321 +
 322 +#define MMU_AP_Limited     0x000  /* Limited access */
 323 +#define MMU_AP_Supervisor  0x400  /* Supervisor RW, User none */
 324 +#define MMU_AP_UserRead    0x800  /* Supervisor RW, User read only */
 325 +#define MMU_AP_Any         0xC00  /* Supervisor RW, User RW */
 326 +
 327 +#define MMU_AP_ap0_Any     0x030
 328 +#define MMU_AP_ap1_Any     0x0C0
 329 +#define MMU_AP_ap2_Any     0x300
 330 +#define MMU_AP_ap3_Any     0xC00
 331 +#define MMU_AP_All (MMU_AP_ap0_Any|MMU_AP_ap1_Any|MMU_AP_ap2_Any|MMU_AP_ap3_Any)
 332 +
 333 +#define MMU_DOMAIN(x)      ((x)<<5)
 334 +
 335 +#define MMU_PAGE_SIZE      0x1000
 336 +#define MMU_SECTION_SIZE   0x100000
 337 +
 338 +#define MMU_CP               p15      /* Co-processor ID */
 339 +#define MMU_Control          c1       /* Control register */
 340 +#define MMU_Base             c2       /* Page tables base */
 341 +#define MMU_DomainAccess     c3       /* Domain access control */
 342 +#define MMU_FaultStatus      c5       /* Fault status register */
 343 +#define MMU_FaultAddress     c6       /* Fault Address */
 344 +#define MMU_InvalidateCache  c7       /* Invalidate cache data */
 345 +#define MMU_TLB              c8       /* Translation Lookaside Buffer */
 346 +
 347 +/* These seem to be 710 specific */
 348 +#define MMU_FlushTLB         c5
 349 +#define MMU_FlushIDC         c7
 350 +
 351 +#define MMU_Control_M  0x001    /* Enable MMU */
 352 +#define MMU_Control_A  0x002    /* Enable address alignment faults */
 353 +#define MMU_Control_C  0x004    /* Enable cache */
 354 +#define MMU_Control_W  0x008    /* Enable write-buffer */
 355 +#define MMU_Control_P  0x010    /* Compatability: 32 bit code */
 356 +#define MMU_Control_D  0x020    /* Compatability: 32 bit data */
 357 +#define MMU_Control_L  0x040    /* Compatability: */
 358 +#define MMU_Control_B  0x080    /* Enable Big-Endian */
 359 +#define MMU_Control_S  0x100    /* Enable system protection */
 360 +#define MMU_Control_R  0x200    /* Enable ROM protection */
 361 +#define MMU_Control_I  0x1000   /* Enable Instruction cache */
 362 +#define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
 363 +#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
 364 +
 365 +/* Extras for some newer versions eg. ARM920 with architecture version 4. */
 366 +#define MMU_Control_F  0x400    /* IMPLEMENTATION DEFINED */
 367 +#define MMU_Control_Z  0x800    /* Enable branch predicion */
 368 +#define MMU_Control_RR 0x4000   /* Select non-random cache replacement */
 369 +
 370 +#endif
 371 diff --git a/include/asm-arm/proc b/include/asm-arm/proc
 372 new file mode 120000
 373 index 0000000..c7f3c20
 374 --- /dev/null
 375 +++ b/include/asm-arm/proc
 376 @@ -0,0 +1 @@
 377 +proc-armv
 378 \ No newline at end of file
 379 diff --git a/include/configs/mx35_3stack.h b/include/configs/mx35_3stack.h
 380 index 4140a86..7b3f1db 100644
 381 --- a/include/configs/mx35_3stack.h
 382 +++ b/include/configs/mx35_3stack.h
 383 @@ -148,6 +148,8 @@
 384   */
 385  #define CONFIG_SYS_LONGHELP    /* undef to save memory */
 386  #define CONFIG_SYS_PROMPT      "MX35 U-Boot > "
 387 +#define CONFIG_ARCH_CPU_INIT
 388 +#define CONFIG_ARCH_MMU
 389  #define CONFIG_AUTO_COMPLETE
 390  #define CONFIG_SYS_CBSIZE      256     /* Console I/O Buffer Size */
 391  /* Print Buffer Size */
 392 --
 393 1.5.4.4
 394