patches/0059-ENGR00119224-mmu-support-for-mx51-3stack-and-mx51-b.patch

   1 From 53f07baf9167201943561651ba9f3587f1b8edc9 Mon Sep 17 00:00:00 2001
   2 From: Terry Lv <r65388@freescale.com>
   3 Date: Fri, 11 Dec 2009 15:19:57 +0800
   4 Subject: [PATCH] ENGR00119224: mmu support for mx51 3stack and mx51 bbg
   5
   6 mmu support for mx51 3stack and mx51 bbg.
   7
   8 Signed-off-by: Terry Lv <r65388@freescale.com>
   9 ---
  10  board/freescale/mx51_3stack/mx51_3stack.c |   71 ++++++++++++++++++++++++++++-
  11  board/freescale/mx51_bbg/flash_header.S   |    3 +-
  12  board/freescale/mx51_bbg/mx51_bbg.c       |   62 +++++++++++++++++++++++++
  13  cpu/arm_cortexa8/mx51/generic.c           |    8 +++
  14  cpu/arm_cortexa8/start.S                  |    3 +
  15  include/configs/mx51_3stack.h             |    3 +
  16  include/configs/mx51_3stack_android.h     |    3 +
  17  include/configs/mx51_bbg.h                |    3 +
  18  include/configs/mx51_bbg_android.h        |    3 +
  19  9 files changed, 155 insertions(+), 4 deletions(-)
  20
  21 diff --git a/board/freescale/mx51_3stack/mx51_3stack.c b/board/freescale/mx51_3stack/mx51_3stack.c
  22 index 38eed4f..0ed1ccb 100644
  23 --- a/board/freescale/mx51_3stack/mx51_3stack.c
  24 +++ b/board/freescale/mx51_3stack/mx51_3stack.c
  25 @@ -29,7 +29,6 @@
  26  #include <asm/arch/mx51_pins.h>
  27  #include <asm/arch/iomux.h>
  28  #include <i2c.h>
  29 -#include <mxc_keyb.h>
  30  #include <asm/arch/keypad.h>
  31  #include "board-mx51_3stack.h"
  32  #include <netdev.h>
  33 @@ -39,7 +38,13 @@
  34  #include <fsl_esdhc.h>
  35  #endif
  36
  37 +#ifdef CONFIG_ARCH_MMU
  38 +#include <asm/mmu.h>
  39 +#include <asm/arch/mmu.h>
  40 +#endif
  41 +
  42  #ifdef CONFIG_FSL_ANDROID
  43 +#include <mxc_keyb.h>
  44  #include <part.h>
  45  #include <ext2fs.h>
  46  #include <linux/mtd/mtd.h>
  47 @@ -130,6 +135,66 @@ inline int is_soc_rev(int rev)
  48         return (system_rev & 0xFF) - rev;
  49  }
  50
  51 +#ifdef CONFIG_ARCH_MMU
  52 +void board_mmu_init(void)
  53 +{
  54 +       unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
  55 +       unsigned long i;
  56 +
  57 +       /*
  58 +       * Set the TTB register
  59 +       */
  60 +       asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
  61 +
  62 +       /*
  63 +       * Set the Domain Access Control Register
  64 +       */
  65 +       i = ARM_ACCESS_DACR_DEFAULT;
  66 +       asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
  67 +
  68 +       /*
  69 +       * First clear all TT entries - ie Set them to Faulting
  70 +       */
  71 +       memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
  72 +       /* Actual   Virtual  Size   Attributes          Function */
  73 +       /* Base     Base     MB     cached? buffered?  access permissions */
  74 +       /* xxx00000 xxx00000 */
  75 +       X_ARM_MMU_SECTION(0x000, 0x200, 0x1,
  76 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  77 +                       ARM_ACCESS_PERM_RW_RW); /* ROM */
  78 +       X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001,
  79 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  80 +                       ARM_ACCESS_PERM_RW_RW); /* IRAM */
  81 +       X_ARM_MMU_SECTION(0x300, 0x300, 0x100,
  82 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  83 +                       ARM_ACCESS_PERM_RW_RW); /* GPU */
  84 +       X_ARM_MMU_SECTION(0x400, 0x400, 0x200,
  85 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  86 +                       ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
  87 +       X_ARM_MMU_SECTION(0x600, 0x600, 0x300,
  88 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  89 +                       ARM_ACCESS_PERM_RW_RW); /* periperals */
  90 +       X_ARM_MMU_SECTION(0x900, 0x000, 0x080,
  91 +                       ARM_CACHEABLE, ARM_BUFFERABLE,
  92 +                       ARM_ACCESS_PERM_RW_RW); /* SDRAM */
  93 +       X_ARM_MMU_SECTION(0x900, 0x900, 0x080,
  94 +                       ARM_CACHEABLE, ARM_BUFFERABLE,
  95 +                       ARM_ACCESS_PERM_RW_RW); /* SDRAM */
  96 +       X_ARM_MMU_SECTION(0x900, 0x980, 0x080,
  97 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  98 +                       ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
  99 +       X_ARM_MMU_SECTION(0xA00, 0xA00, 0x100,
 100 +                       ARM_CACHEABLE, ARM_BUFFERABLE,
 101 +                       ARM_ACCESS_PERM_RW_RW); /* SDRAM */
 102 +       X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10,
 103 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 104 +                       ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
 105 +       X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040,
 106 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 107 +                       ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
 108 +}
 109 +#endif
 110 +
 111  int dram_init(void)
 112  {
 113         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 114 @@ -781,7 +846,7 @@ static int check_nand_recovery_cmd_file(char *mtd_part_name,
 115
 116  static int check_recovery_cmd_file(void)
 117  {
 118 -       int if_exist;
 119 +       int if_exist = 0;
 120         char *env = NULL;
 121
 122         switch (get_boot_device()) {
 123 @@ -803,9 +868,11 @@ static int check_recovery_cmd_file(void)
 124                 if (!env)
 125                         setenv("partition", MTD_ACTIVE_PART);
 126
 127 +               /*
 128                 if_exist = check_nand_recovery_cmd_file(CONFIG_ANDROID_UBIFS_PARTITION_NM,
 129                                                 CONFIG_ANDROID_CACHE_PARTITION_NAND,
 130                                                 CONFIG_ANDROID_RECOVERY_CMD_FILE);
 131 +               */
 132                 break;
 133         case SPI_NOR_BOOT:
 134                 return 0;
 135 diff --git a/board/freescale/mx51_bbg/flash_header.S b/board/freescale/mx51_bbg/flash_header.S
 136 index 6790679..17a5c59 100644
 137 --- a/board/freescale/mx51_bbg/flash_header.S
 138 +++ b/board/freescale/mx51_bbg/flash_header.S
 139 @@ -108,6 +108,5 @@ MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
 140  MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
 141  MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
 142  dcd_data_end:
 143 -image_len:             .word   0x100000
 144 -//image_len:           .word   _end - _start
 145 +image_len:             .word   __u_boot_cmd_end - TEXT_BASE
 146  #endif
 147 diff --git a/board/freescale/mx51_bbg/mx51_bbg.c b/board/freescale/mx51_bbg/mx51_bbg.c
 148 index 8a45a78..4279ac6 100644
 149 --- a/board/freescale/mx51_bbg/mx51_bbg.c
 150 +++ b/board/freescale/mx51_bbg/mx51_bbg.c
 151 @@ -41,6 +41,11 @@
 152  #include <fsl_esdhc.h>
 153  #endif
 154
 155 +#ifdef CONFIG_ARCH_MMU
 156 +#include <asm/mmu.h>
 157 +#include <asm/arch/mmu.h>
 158 +#endif
 159 +
 160  #ifdef CONFIG_FSL_ANDROID
 161  #include <mxc_keyb.h>
 162  #include <part.h>
 163 @@ -140,6 +145,63 @@ inline int is_soc_rev(int rev)
 164         return (system_rev & 0xFF) - rev;
 165  }
 166
 167 +#ifdef CONFIG_ARCH_MMU
 168 +void board_mmu_init(void)
 169 +{
 170 +       unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
 171 +       unsigned long i;
 172 +
 173 +       /*
 174 +       * Set the TTB register
 175 +       */
 176 +       asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
 177 +
 178 +       /*
 179 +       * Set the Domain Access Control Register
 180 +       */
 181 +       i = ARM_ACCESS_DACR_DEFAULT;
 182 +       asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
 183 +
 184 +       /*
 185 +       * First clear all TT entries - ie Set them to Faulting
 186 +       */
 187 +       memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
 188 +       /* Actual   Virtual  Size   Attributes          Function */
 189 +       /* Base     Base     MB     cached? buffered?  access permissions */
 190 +       /* xxx00000 xxx00000 */
 191 +       X_ARM_MMU_SECTION(0x000, 0x200, 0x1,
 192 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 193 +                       ARM_ACCESS_PERM_RW_RW); /* ROM */
 194 +       X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001,
 195 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 196 +                       ARM_ACCESS_PERM_RW_RW); /* IRAM */
 197 +       X_ARM_MMU_SECTION(0x300, 0x300, 0x100,
 198 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 199 +                       ARM_ACCESS_PERM_RW_RW); /* GPU */
 200 +       X_ARM_MMU_SECTION(0x400, 0x400, 0x200,
 201 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 202 +                       ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
 203 +       X_ARM_MMU_SECTION(0x600, 0x600, 0x300,
 204 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 205 +                       ARM_ACCESS_PERM_RW_RW); /* periperals */
 206 +       X_ARM_MMU_SECTION(0x900, 0x000, 0x1FF,
 207 +                       ARM_CACHEABLE, ARM_BUFFERABLE,
 208 +                       ARM_ACCESS_PERM_RW_RW); /* SDRAM */
 209 +       X_ARM_MMU_SECTION(0x900, 0x900, 0x200,
 210 +                       ARM_CACHEABLE, ARM_BUFFERABLE,
 211 +                       ARM_ACCESS_PERM_RW_RW); /* SDRAM */
 212 +       X_ARM_MMU_SECTION(0x900, 0xE00, 0x200,
 213 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 214 +                       ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
 215 +       X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10,
 216 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 217 +                       ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
 218 +       X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040,
 219 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 220 +                       ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
 221 +}
 222 +#endif
 223 +
 224  int dram_init(void)
 225  {
 226         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 227 diff --git a/cpu/arm_cortexa8/mx51/generic.c b/cpu/arm_cortexa8/mx51/generic.c
 228 index 2512081..a073de1 100644
 229 --- a/cpu/arm_cortexa8/mx51/generic.c
 230 +++ b/cpu/arm_cortexa8/mx51/generic.c
 231 @@ -260,3 +260,11 @@ int cpu_eth_init(bd_t *bis)
 232         return rc;
 233  }
 234
 235 +#if defined(CONFIG_ARCH_CPU_INIT)
 236 +int arch_cpu_init(void)
 237 +{
 238 +       icache_enable();
 239 +       dcache_enable();
 240 +       return 0;
 241 +}
 242 +#endif
 243 diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa8/start.S
 244 index 4983a47..4bbb56a 100644
 245 --- a/cpu/arm_cortexa8/start.S
 246 +++ b/cpu/arm_cortexa8/start.S
 247 @@ -178,6 +178,9 @@ clbss_l:
 248         add     r0, r0, #4              @ increment clear index pointer
 249         bne     clbss_l                 @ keep clearing till at end
 250
 251 +#ifdef CONFIG_ARCH_MMU
 252 +       bl board_mmu_init
 253 +#endif
 254         ldr     pc, _start_armboot      @ jump to C code
 255
 256  _start_armboot: .word start_armboot
 257 diff --git a/include/configs/mx51_3stack.h b/include/configs/mx51_3stack.h
 258 index 29f30da..3cecd58 100644
 259 --- a/include/configs/mx51_3stack.h
 260 +++ b/include/configs/mx51_3stack.h
 261 @@ -41,6 +41,9 @@
 262
 263  #define CONFIG_MX51_HCLK_FREQ  24000000        /* RedBoot says 26MHz */
 264
 265 +#define CONFIG_ARCH_CPU_INIT
 266 +#define CONFIG_ARCH_MMU
 267 +
 268  #define CONFIG_DISPLAY_CPUINFO
 269  #define CONFIG_DISPLAY_BOARDINFO
 270
 271 diff --git a/include/configs/mx51_3stack_android.h b/include/configs/mx51_3stack_android.h
 272 index ed0611b..53dd409 100644
 273 --- a/include/configs/mx51_3stack_android.h
 274 +++ b/include/configs/mx51_3stack_android.h
 275 @@ -37,6 +37,9 @@
 276  #define CONFIG_FLASH_HEADER_OFFSET 0x400
 277  #define CONFIG_FLASH_HEADER_BARKER 0xB1
 278
 279 +#define CONFIG_ARCH_CPU_INIT
 280 +#define CONFIG_ARCH_MMU
 281 +
 282  #define CONFIG_SKIP_RELOCATE_UBOOT
 283
 284  #define CONFIG_MX51_HCLK_FREQ  24000000        /* RedBoot says 26MHz */
 285 diff --git a/include/configs/mx51_bbg.h b/include/configs/mx51_bbg.h
 286 index 8ef891f..c5c3ae9 100644
 287 --- a/include/configs/mx51_bbg.h
 288 +++ b/include/configs/mx51_bbg.h
 289 @@ -40,6 +40,9 @@
 290
 291  #define CONFIG_MX51_HCLK_FREQ  24000000        /* RedBoot says 26MHz */
 292
 293 +#define CONFIG_ARCH_CPU_INIT
 294 +#define CONFIG_ARCH_MMU
 295 +
 296  #define CONFIG_DISPLAY_CPUINFO
 297  #define CONFIG_DISPLAY_BOARDINFO
 298
 299 diff --git a/include/configs/mx51_bbg_android.h b/include/configs/mx51_bbg_android.h
 300 index ea1998c..d2cccbc 100644
 301 --- a/include/configs/mx51_bbg_android.h
 302 +++ b/include/configs/mx51_bbg_android.h
 303 @@ -37,6 +37,9 @@
 304  #define CONFIG_FLASH_HEADER_OFFSET 0x400
 305  #define CONFIG_FLASH_HEADER_BARKER 0xB1
 306
 307 +#define CONFIG_ARCH_CPU_INIT
 308 +#define CONFIG_ARCH_MMU
 309 +
 310  #define CONFIG_SKIP_RELOCATE_UBOOT
 311
 312  #define CONFIG_MX51_HCLK_FREQ  24000000        /* RedBoot says 26MHz */
 313 --
 314 1.5.4.4
 315