patches/0062-ENGR00119254-Add-mmu-header-for-mx51-build-error.patch

   1 From f6afbf15365eec4c2f7702d79920dcf2f47fe48c Mon Sep 17 00:00:00 2001
   2 From: Terry Lv <r65388@freescale.com>
   3 Date: Fri, 11 Dec 2009 19:12:06 +0800
   4 Subject: [PATCH] ENGR00119254: Add mmu header for mx51 build error
   5
   6 Add mmu header for mx51 build error.
   7
   8 Signed-off-by: Terry Lv <r65388@freescale.com>
   9 ---
  10  include/asm-arm/arch-mx51/mmu.h |  135 +++++++++++++++++++++++++++++++++++++++
  11  1 files changed, 135 insertions(+), 0 deletions(-)
  12
  13 diff --git a/include/asm-arm/arch-mx51/mmu.h b/include/asm-arm/arch-mx51/mmu.h
  14 new file mode 100644
  15 index 0000000..a701c72
  16 --- /dev/null
  17 +++ b/include/asm-arm/arch-mx51/mmu.h
  18 @@ -0,0 +1,135 @@
  19 +/*
  20 + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  21 + */
  22 +
  23 +/*
  24 + * The code contained herein is licensed under the GNU General Public
  25 + * License. You may obtain a copy of the GNU General Public License
  26 + * Version 2 or later at the following locations:
  27 + *
  28 + * http://www.opensource.org/licenses/gpl-license.html
  29 + * http://www.gnu.org/copyleft/gpl.html
  30 + */
  31 +
  32 +#ifndef __ARM_ARCH_MMU_H
  33 +#define __ARM_ARCH_MMU_H
  34 +
  35 +/*
  36 + * Translation Table Base Bit Masks
  37 + */
  38 +#define ARM_TRANSLATION_TABLE_MASK               0xFFFFC000
  39 +
  40 +/*
  41 + * Domain Access Control Bit Masks
  42 + */
  43 +#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)    (0x0 << (domain_num)*2)
  44 +#define ARM_ACCESS_TYPE_CLIENT(domain_num)       (0x1 << (domain_num)*2)
  45 +#define ARM_ACCESS_TYPE_MANAGER(domain_num)      (0x3 << (domain_num)*2)
  46 +
  47 +struct ARM_MMU_FIRST_LEVEL_FAULT {
  48 +       unsigned int id:2;
  49 +       unsigned int sbz:30;
  50 +};
  51 +
  52 +#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
  53 +
  54 +struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
  55 +       unsigned int id:2;
  56 +       unsigned int imp:2;
  57 +       unsigned int domain:4;
  58 +       unsigned int sbz:1;
  59 +       unsigned int base_address:23;
  60 +};
  61 +
  62 +#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
  63 +
  64 +struct ARM_MMU_FIRST_LEVEL_SECTION {
  65 +       unsigned int id:2;
  66 +       unsigned int b:1;
  67 +       unsigned int c:1;
  68 +       unsigned int imp:1;
  69 +       unsigned int domain:4;
  70 +       unsigned int sbz0:1;
  71 +       unsigned int ap:2;
  72 +       unsigned int sbz1:8;
  73 +       unsigned int base_address:12;
  74 +};
  75 +
  76 +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
  77 +
  78 +struct ARM_MMU_FIRST_LEVEL_RESERVED {
  79 +       unsigned int id:2;
  80 +       unsigned int sbz:30;
  81 +};
  82 +
  83 +#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
  84 +
  85 +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
  86 +       (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
  87 +
  88 +#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
  89 +
  90 +#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,           \
  91 +                       cacheable, bufferable, perm)                    \
  92 +       {                                                               \
  93 +       register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;             \
  94 +       desc.word = 0;                                                  \
  95 +       desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;               \
  96 +       desc.section.domain = 0;                                        \
  97 +       desc.section.c = (cacheable);                                   \
  98 +       desc.section.b = (bufferable);                                  \
  99 +       desc.section.ap = (perm);                                       \
 100 +       desc.section.base_address = (actual_base);                      \
 101 +       *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
 102 +                               = desc.word;                            \
 103 +       }
 104 +
 105 +#define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access)     \
 106 +       {                                                               \
 107 +               int i; int j = abase; int k = vbase;                    \
 108 +               for (i = size; i > 0 ; i--, j++, k++)                   \
 109 +                       ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
 110 +       }
 111 +
 112 +union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
 113 +       unsigned long word;
 114 +       struct ARM_MMU_FIRST_LEVEL_FAULT fault;
 115 +       struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
 116 +       struct ARM_MMU_FIRST_LEVEL_SECTION section;
 117 +       struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
 118 +};
 119 +
 120 +#define ARM_UNCACHEABLE                0
 121 +#define ARM_CACHEABLE          1
 122 +#define ARM_UNBUFFERABLE       0
 123 +#define ARM_BUFFERABLE         1
 124 +
 125 +#define ARM_ACCESS_PERM_NONE_NONE      0
 126 +#define ARM_ACCESS_PERM_RO_NONE                0
 127 +#define ARM_ACCESS_PERM_RO_RO          0
 128 +#define ARM_ACCESS_PERM_RW_NONE                1
 129 +#define ARM_ACCESS_PERM_RW_RO          2
 130 +#define ARM_ACCESS_PERM_RW_RW          3
 131 +
 132 +/*
 133 + * Initialization for the Domain Access Control Register
 134 + */
 135 +#define ARM_ACCESS_DACR_DEFAULT      ( \
 136 +       ARM_ACCESS_TYPE_MANAGER(0)    | \
 137 +       ARM_ACCESS_TYPE_NO_ACCESS(1)  | \
 138 +       ARM_ACCESS_TYPE_NO_ACCESS(2)  | \
 139 +       ARM_ACCESS_TYPE_NO_ACCESS(3)  | \
 140 +       ARM_ACCESS_TYPE_NO_ACCESS(4)  | \
 141 +       ARM_ACCESS_TYPE_NO_ACCESS(5)  | \
 142 +       ARM_ACCESS_TYPE_NO_ACCESS(6)  | \
 143 +       ARM_ACCESS_TYPE_NO_ACCESS(7)  | \
 144 +       ARM_ACCESS_TYPE_NO_ACCESS(8)  | \
 145 +       ARM_ACCESS_TYPE_NO_ACCESS(9)  | \
 146 +       ARM_ACCESS_TYPE_NO_ACCESS(10) | \
 147 +       ARM_ACCESS_TYPE_NO_ACCESS(11) | \
 148 +       ARM_ACCESS_TYPE_NO_ACCESS(12) | \
 149 +       ARM_ACCESS_TYPE_NO_ACCESS(13) | \
 150 +       ARM_ACCESS_TYPE_NO_ACCESS(14) | \
 151 +       ARM_ACCESS_TYPE_NO_ACCESS(15))
 152 +
 153 +#endif
 154 --
 155 1.5.4.4
 156