patches/0073-ENGR00119738-eMMC-card-access-failed.patch

   1 From a7b772a9e3f9f565ee8765a07797a3113aef1892 Mon Sep 17 00:00:00 2001
   2 From: Terry Lv <r65388@freescale.com>
   3 Date: Thu, 31 Dec 2009 14:35:16 +0800
   4 Subject: [PATCH] ENGR00119738: eMMC card access failed.
   5
   6 The iomux settings of mx51 bbg and mx35 3stack can't support eMMC card.
   7 Thus, change the iomux settings.
   8
   9 Signed-off-by: Terry Lv <r65388@freescale.com>
  10 ---
  11  board/freescale/mx35_3stack/mx35_3stack.c |   26 +++++++++---------
  12  board/freescale/mx51_bbg/mx51_bbg.c       |   43 +++++++++++++++++++++-------
  13  2 files changed, 45 insertions(+), 24 deletions(-)
  14
  15 diff --git a/board/freescale/mx35_3stack/mx35_3stack.c b/board/freescale/mx35_3stack/mx35_3stack.c
  16 index 4f79942..1186368 100644
  17 --- a/board/freescale/mx35_3stack/mx35_3stack.c
  18 +++ b/board/freescale/mx35_3stack/mx35_3stack.c
  19 @@ -380,18 +380,18 @@ int esdhc_gpio_init(void)
  20                                 (u32 *)MMC_SDHC1_BASE_ADDR;
  21
  22                 pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
  23 -                               PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
  24 -                               PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
  25 -               mxc_request_iomux(MX35_PIN_SD1_CLK,
  26 -                               MUX_CONFIG_FUNC | MUX_CONFIG_SION);
  27 -               mxc_iomux_set_pad(MX35_PIN_SD1_CLK, pad_val);
  28 -
  29 -               pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
  30                         PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
  31 -                       PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
  32 +                       PAD_CTL_100K_PD | PAD_CTL_SRE_FAST;
  33                 mxc_request_iomux(MX35_PIN_SD1_CMD,
  34                         MUX_CONFIG_FUNC | MUX_CONFIG_SION);
  35                 mxc_iomux_set_pad(MX35_PIN_SD1_CMD, pad_val);
  36 +
  37 +               pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
  38 +                               PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
  39 +                               PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
  40 +               mxc_request_iomux(MX35_PIN_SD1_CLK,
  41 +                               MUX_CONFIG_FUNC | MUX_CONFIG_SION);
  42 +               mxc_iomux_set_pad(MX35_PIN_SD1_CLK, pad_val);
  43                 mxc_request_iomux(MX35_PIN_SD1_DATA0,
  44                           MUX_CONFIG_FUNC);
  45                 mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, pad_val);
  46 @@ -415,13 +415,13 @@ int esdhc_gpio_init(void)
  47
  48                 pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
  49                         PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
  50 -                       PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
  51 -               mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val);
  52 +                       PAD_CTL_100K_PD | PAD_CTL_SRE_FAST;
  53 +               mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val);
  54
  55                 pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
  56 -                       PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
  57 -                       PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
  58 -               mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val);
  59 +                               PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
  60 +                               PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
  61 +               mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val);
  62                 mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val);
  63                 mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val);
  64
  65 diff --git a/board/freescale/mx51_bbg/mx51_bbg.c b/board/freescale/mx51_bbg/mx51_bbg.c
  66 index 60fc704..e5ac369 100644
  67 --- a/board/freescale/mx51_bbg/mx51_bbg.c
  68 +++ b/board/freescale/mx51_bbg/mx51_bbg.c
  69 @@ -568,13 +568,10 @@ int esdhc_gpio_init(void)
  70         case 0:
  71                 imx_esdhc_base_addr = (u32 *)MMC_SDHC1_BASE_ADDR;
  72
  73 -               pad = PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
  74 -                               PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
  75 -
  76                 mxc_request_iomux(MX51_PIN_SD1_CMD,
  77 -                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
  78 +                               IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
  79                 mxc_request_iomux(MX51_PIN_SD1_CLK,
  80 -                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
  81 +                               IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
  82
  83                 mxc_request_iomux(MX51_PIN_SD1_DATA0,
  84                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
  85 @@ -584,12 +581,36 @@ int esdhc_gpio_init(void)
  86                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
  87                 mxc_request_iomux(MX51_PIN_SD1_DATA3,
  88                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
  89 -               mxc_iomux_set_pad(MX51_PIN_SD1_CMD, pad);
  90 -               mxc_iomux_set_pad(MX51_PIN_SD1_CLK, pad);
  91 -               mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, pad);
  92 -               mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, pad);
  93 -               mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, pad);
  94 -               mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, pad);
  95 +               mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
  96 +                               PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
  97 +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
  98 +                               PAD_CTL_PUE_PULL |
  99 +                               PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 100 +               mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 101 +                               PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 102 +                               PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
 103 +                               PAD_CTL_PUE_PULL |
 104 +                               PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 105 +               mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 106 +                               PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 107 +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 108 +                               PAD_CTL_PUE_PULL |
 109 +                               PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 110 +               mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 111 +                               PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 112 +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 113 +                               PAD_CTL_PUE_PULL |
 114 +                               PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 115 +               mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 116 +                               PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 117 +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 118 +                               PAD_CTL_PUE_PULL |
 119 +                               PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 120 +               mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 121 +                               PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 122 +                               PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
 123 +                               PAD_CTL_PUE_PULL |
 124 +                               PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 125                 break;
 126         case 1:
 127                 imx_esdhc_base_addr = (u32 *)MMC_SDHC2_BASE_ADDR;
 128 --
 129 1.5.4.4
 130