1 From 762d994929deb79569986bda8e4d7b56e06d14f0 Mon Sep 17 00:00:00 2001
2 From: Jason <r64343@freescale.com>
3 Date: Wed, 17 Mar 2010 16:41:56 +0800
4 Subject: [PATCH] ENGR00121202 Add uboot support for MX53
6 Add uboot support for MX53
8 Signed-off-by:Jason Liu <r64343@freescale.com>
11 board/freescale/mx53_evk/Makefile | 49 ++
12 board/freescale/mx53_evk/config.mk | 3 +
13 board/freescale/mx53_evk/flash_header.S | 124 +++++
14 board/freescale/mx53_evk/lowlevel_init.S | 216 +++++++++
15 board/freescale/mx53_evk/mx53_evk.c | 449 ++++++++++++++++++
16 board/freescale/mx53_evk/u-boot.lds | 73 +++
17 cpu/arm_cortexa8/Makefile | 2 +-
18 cpu/arm_cortexa8/mx53/Makefile | 48 ++
19 cpu/arm_cortexa8/mx53/cache.c | 44 ++
20 cpu/arm_cortexa8/mx53/crm_regs.h | 750 ++++++++++++++++++++++++++++++
21 cpu/arm_cortexa8/mx53/generic.c | 347 ++++++++++++++
22 cpu/arm_cortexa8/mx53/interrupts.c | 39 ++
23 cpu/arm_cortexa8/mx53/iomux.c | 148 ++++++
24 cpu/arm_cortexa8/mx53/serial.c | 226 +++++++++
25 cpu/arm_cortexa8/mx53/timer.c | 127 +++++
26 drivers/i2c/mxc_i2c.c | 4 +-
27 drivers/net/mxc_fec.c | 5 +-
28 include/asm-arm/arch-mx53/imx_spi_nor.h | 70 +++
29 include/asm-arm/arch-mx53/iomux.h | 249 ++++++++++
30 include/asm-arm/arch-mx53/mx53.h | 422 +++++++++++++++++
31 include/asm-arm/arch-mx53/mx53_pins.h | 374 +++++++++++++++
32 include/asm-arm/mach-types.h | 13 +
33 include/configs/mx53_evk.h | 225 +++++++++
34 24 files changed, 4007 insertions(+), 3 deletions(-)
36 diff --git a/Makefile b/Makefile
37 index 2437539..eeb958a 100644
40 @@ -3254,6 +3254,9 @@ mx51_3stack_android_config \
41 mx51_3stack_config : unconfig
42 @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51_3stack freescale mx51
44 +mx53_evk_config : unconfig
45 + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_evk freescale mx53
47 omap2420h4_config : unconfig
48 @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
50 diff --git a/board/freescale/mx53_evk/Makefile b/board/freescale/mx53_evk/Makefile
52 index 0000000..9e20903
54 +++ b/board/freescale/mx53_evk/Makefile
57 +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
59 +# (C) Copyright 2010 Freescale Semiconductor, Inc.
61 +# This program is free software; you can redistribute it and/or
62 +# modify it under the terms of the GNU General Public License as
63 +# published by the Free Software Foundation; either version 2 of
64 +# the License, or (at your option) any later version.
66 +# This program is distributed in the hope that it will be useful,
67 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
68 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
69 +# GNU General Public License for more details.
71 +# You should have received a copy of the GNU General Public License
72 +# along with this program; if not, write to the Free Software
73 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
77 +include $(TOPDIR)/config.mk
79 +LIB = $(obj)lib$(BOARD).a
82 +SOBJS := lowlevel_init.o flash_header.o
84 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
85 +OBJS := $(addprefix $(obj),$(COBJS))
86 +SOBJS := $(addprefix $(obj),$(SOBJS))
88 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
89 + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
92 + rm -f $(SOBJS) $(OBJS)
95 + rm -f $(LIB) core *.bak .depend
97 +#########################################################################
99 +# defines $(obj).depend target
100 +include $(SRCTREE)/rules.mk
102 +sinclude $(obj).depend
104 +#########################################################################
105 diff --git a/board/freescale/mx53_evk/config.mk b/board/freescale/mx53_evk/config.mk
107 index 0000000..34f830a
109 +++ b/board/freescale/mx53_evk/config.mk
111 +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
113 +TEXT_BASE = 0x77800000
114 diff --git a/board/freescale/mx53_evk/flash_header.S b/board/freescale/mx53_evk/flash_header.S
116 index 0000000..4e88068
118 +++ b/board/freescale/mx53_evk/flash_header.S
121 + * Copyright (C) 2010 Freescale Semiconductor, Inc.
123 + * This program is free software; you can redistribute it and/or
124 + * modify it under the terms of the GNU General Public License as
125 + * published by the Free Software Foundation; either version 2 of
126 + * the License, or (at your option) any later version.
128 + * This program is distributed in the hope that it will be useful,
129 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
130 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
131 + * GNU General Public License for more details.
133 + * You should have received a copy of the GNU General Public License
134 + * along with this program; if not, write to the Free Software
135 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
136 + * MA 02111-1307 USA
140 +#include <asm/arch/mx53.h>
142 +#ifdef CONFIG_FLASH_HEADER
143 +#ifndef CONFIG_FLASH_HEADER_OFFSET
144 +# error "Must define the offset of flash header"
147 +#define CPU_2_BE_32(l) \
148 + ((((l) & 0x000000FF) << 24) | \
149 + (((l) & 0x0000FF00) << 8) | \
150 + (((l) & 0x00FF0000) >> 8) | \
151 + (((l) & 0xFF000000) >> 24))
153 +#define MXC_DCD_ITEM(i, addr, val) \
155 + .word CPU_2_BE_32(addr) ; \
156 + .word CPU_2_BE_32(val) ; \
158 +.section ".text.flasheader", "x"
160 + .org CONFIG_FLASH_HEADER_OFFSET
161 +ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
162 +app_code_jump_v: .word _start
164 +dcd_ptr: .word dcd_hdr
165 +boot_data_ptr: .word boot_data
166 +self_ptr: .word ivt_header
167 +app_code_csf: .word 0x0
170 +boot_data: .word 0x77800000
171 +image_len: .word 256 * 1024
174 +dcd_hdr: .word 0x401002D2 /* Tag=0xD2, Len=65*8 + 4 + 4, Ver=0x40 */
175 +write_dcd_cmd: .word 0x040C02CC /* Tag=0xCC, Len=65*8 + 4, Param=4 */
178 +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00380000)
179 +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00380040)
180 +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x72c, 0x00380000)
181 +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x560, 0x00380000)
182 +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00380040)
183 +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x728, 0x00380000)
184 +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x594, 0x00380000)
185 +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x590, 0x00380040)
186 +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x71c, 0x00380000)
187 +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x584, 0x00380000)
188 +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x57c, 0x00380040)
189 +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x718, 0x00380000)
190 +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x564, 0x00380040)
191 +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x574, 0x00380000)
192 +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x570, 0x00380000)
193 +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x578, 0x00380000)
194 +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x580, 0x00380040)
195 +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x588, 0x00380000)
196 +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x6f0, 0x00380000)
197 +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200)
198 +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000)
199 +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x714, 0x00000000)
200 +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x720, 0x00380000)
201 +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x724, 0x06000000)
202 +MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x88, 0x2b2f3031)
203 +MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x90, 0x40363333)
204 +MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0xF8, 0x00000800)
205 +MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x7c, 0x01310132)
206 +MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x80, 0x0133014b)
207 +MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x18, 0x000016d0)
208 +MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x00, 0xc4110000)
209 +MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x98, 0x00000f00)
210 +MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x0C, 0x4d5122d2)
211 +MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x10, 0x92d18a22)
212 +MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x14, 0x00c70092)
213 +MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x2c, 0x000026d2)
214 +MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x30, 0x009f000e)
215 +MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x08, 0x12272000)
216 +MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x04, 0x00030012)
217 +MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x1c, 0x04008010)
218 +MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x1c, 0x00008032)
219 +MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x1c, 0x00008033)
220 +MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x1c, 0x00008031)
221 +MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x1c, 0x0b5280b0)
222 +MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x1c, 0x04008010)
223 +MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x1c, 0x00008020)
224 +MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x1c, 0x00008020)
225 +MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x1c, 0x0a528030)
226 +MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x1c, 0x03c68031)
227 +MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x1c, 0x00468031)
228 +MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x1c, 0x04008018)
229 +MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x1c, 0x0000803a)
230 +MXC_DCD_ITEM(53, ESDCTL_BASE_ADDR + 0x1c, 0x0000803b)
231 +MXC_DCD_ITEM(54, ESDCTL_BASE_ADDR + 0x1c, 0x00008039)
232 +MXC_DCD_ITEM(55, ESDCTL_BASE_ADDR + 0x1c, 0x0b528138)
233 +MXC_DCD_ITEM(56, ESDCTL_BASE_ADDR + 0x1c, 0x04008018)
234 +MXC_DCD_ITEM(57, ESDCTL_BASE_ADDR + 0x1c, 0x00008028)
235 +MXC_DCD_ITEM(58, ESDCTL_BASE_ADDR + 0x1c, 0x00008028)
236 +MXC_DCD_ITEM(59, ESDCTL_BASE_ADDR + 0x1c, 0x0a528038)
237 +MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x1c, 0x03c68039)
238 +MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x1c, 0x00468039)
239 +MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x20, 0x00005800)
240 +MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x58, 0x00033337)
241 +MXC_DCD_ITEM(64, ESDCTL_BASE_ADDR + 0x1c, 0x00000000)
242 +MXC_DCD_ITEM(65, ESDCTL_BASE_ADDR + 0x18, 0x00001750)
244 diff --git a/board/freescale/mx53_evk/lowlevel_init.S b/board/freescale/mx53_evk/lowlevel_init.S
246 index 0000000..c67c584
248 +++ b/board/freescale/mx53_evk/lowlevel_init.S
251 + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
253 + * Copyright (C) 2010 Freescale Semiconductor, Inc.
255 + * This program is free software; you can redistribute it and/or
256 + * modify it under the terms of the GNU General Public License as
257 + * published by the Free Software Foundation; either version 2 of
258 + * the License, or (at your option) any later version.
260 + * This program is distributed in the hope that it will be useful,
261 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
262 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
263 + * GNU General Public License for more details.
265 + * You should have received a copy of the GNU General Public License
266 + * along with this program; if not, write to the Free Software
267 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
268 + * MA 02111-1307 USA
272 +#include <asm/arch/mx53.h>
275 + * L2CC Cache setup/invalidation/disable
278 + /* explicitly disable L2 cache */
279 + mrc 15, 0, r0, c1, c0, 1
281 + mcr 15, 0, r0, c1, c0, 1
283 + /* reconfigure L2 cache aux control reg */
284 + mov r0, #0xC0 /* tag RAM */
285 + add r0, r0, #0x4 /* data RAM */
286 + orr r0, r0, #(1 << 24) /* disable write allocate delay */
287 + orr r0, r0, #(1 << 23) /* disable write allocate combine */
288 + orr r0, r0, #(1 << 22) /* disable write allocate */
290 + mcr 15, 1, r0, c9, c0, 2
291 +.endm /* init_l2cc */
293 +/* AIPS setup - Only setup MPROTx registers.
294 + * The PACR default values are good.*/
297 + * Set all MPROTx to be non-bufferable, trusted for R/W,
298 + * not forced to user-mode.
300 + ldr r0, =AIPS1_BASE_ADDR
301 + ldr r1, =0x77777777
304 + ldr r0, =AIPS2_BASE_ADDR
307 +.endm /* init_aips */
309 +.macro setup_pll pll, freq
311 + ldr r1, =0x00001232
312 + str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
314 + str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
316 + str r3, [r2, #PLL_DP_OP]
317 + str r3, [r2, #PLL_DP_HFS_OP]
319 + str r4, [r2, #PLL_DP_MFD]
320 + str r4, [r2, #PLL_DP_HFS_MFD]
322 + str r5, [r2, #PLL_DP_MFN]
323 + str r5, [r2, #PLL_DP_HFS_MFN]
325 + ldr r1, =0x00001232
326 + str r1, [r2, #PLL_DP_CTL]
327 +1: ldr r1, [r2, #PLL_DP_CTL]
333 + ldr r0, CCM_BASE_ADDR_W
335 + /* Switch ARM to step clock */
337 + str r1, [r0, #CLKCTL_CCSR]
340 + mov r4, #DP_MFD_800
341 + mov r5, #DP_MFN_800
342 + setup_pll PLL1_BASE_ADDR, 800
345 + mov r4, #DP_MFD_400
346 + mov r5, #DP_MFN_400
347 + setup_pll PLL3_BASE_ADDR, 400
349 + /* Switch peripheral to PLL3 */
350 + ldr r0, CCM_BASE_ADDR_W
351 + ldr r1, CCM_VAL_0x00015154
352 + str r1, [r0, #CLKCTL_CBCMR]
353 + ldr r1, CCM_VAL_0x02888945
354 + orr r1, r1, #(1 << 16) /* Set DDR divider to run at 200MHz */
355 + str r1, [r0, #CLKCTL_CBCDR]
356 + /* make sure mux & divider change is effective */
357 +1: ldr r1, [r0, #CLKCTL_CDHIPR]
362 + mov r4, #DP_MFD_600
363 + mov r5, #DP_MFN_600
364 + setup_pll PLL2_BASE_ADDR, 600
366 + /* Switch peripheral to PLL2 */
367 + ldr r0, CCM_BASE_ADDR_W
368 + ldr r1, CCM_VAL_0x00809145 /* AHB is 120MHz, from PLL2 */
369 + orr r1, r1, #(1 << 16) /* Set DDR divider to run at 300MHz */
370 + orr r1, r1, #(2 << 19) /* Set AXI_B divider to run at 200MHz */
371 + str r1, [r0, #CLKCTL_CBCDR]
373 + ldr r1, CCM_VAL_0x00016154
374 + str r1, [r0, #CLKCTL_CBCMR]
376 + /* make sure mux change is effective */
377 +1: ldr r1, [r0, #CLKCTL_CDHIPR]
382 + mov r4, #DP_MFD_216
383 + mov r5, #DP_MFN_216
384 + setup_pll PLL3_BASE_ADDR, 216
386 + /* Set the platform clock dividers */
387 + ldr r0, PLATFORM_BASE_ADDR_W
388 + ldr r1, PLATFORM_CLOCK_DIV_W
389 + str r1, [r0, #PLATFORM_ICGC]
392 + ldr r0, CCM_BASE_ADDR_W
394 + str r1, [r0, #CLKCTL_CACRR]
396 + /* Switch ARM back to PLL 1. */
398 + str r1, [r0, #CLKCTL_CCSR]
400 + ldr r1, [r0, #CLKCTL_CSCDR1]
404 + str r1, [r0, #CLKCTL_CSCDR1]
406 + /* Restore the default values in the Gate registers */
407 + ldr r1, =0xFFFFFFFF
408 + str r1, [r0, #CLKCTL_CCGR0]
409 + str r1, [r0, #CLKCTL_CCGR1]
410 + str r1, [r0, #CLKCTL_CCGR2]
411 + str r1, [r0, #CLKCTL_CCGR3]
412 + str r1, [r0, #CLKCTL_CCGR4]
413 + str r1, [r0, #CLKCTL_CCGR5]
414 + str r1, [r0, #CLKCTL_CCGR6]
415 + str r1, [r0, #CLKCTL_CCGR7]
418 + str r1, [r0, #CLKCTL_CCDR]
420 + /* for cko - for ARM div by 8 */
421 + mov r1, #0x000A0000
422 + add r1, r1, #0x00000F0
423 + str r1, [r0, #CLKCTL_CCOSR]
426 +.section ".text.init", "x"
428 +.globl lowlevel_init
431 +#ifdef ENABLE_IMPRECISE_ABORT
432 + mrs r1, spsr /* save old spsr */
433 + mrs r0, cpsr /* read out the cpsr */
434 + bic r0, r0, #0x100 /* clear the A bit */
435 + msr spsr, r0 /* update spsr */
436 + add lr, pc, #0x8 /* update lr */
437 + movs pc, lr /* update cpsr */
442 + msr spsr, r1 /* restore old spsr */
445 + /* ARM errata ID #468414 */
446 + mrc 15, 0, r1, c1, c0, 1
447 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */
448 + mcr 15, 0, r1, c1, c0, 1
458 +/* Board level setting value */
459 +CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
460 +CCM_VAL_0x00016154: .word 0x00016154
461 +CCM_VAL_0x00809145: .word 0x00809145
462 +CCM_VAL_0x00015154: .word 0x00015154
463 +CCM_VAL_0x02888945: .word 0x02888945
464 +PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR
465 +PLATFORM_CLOCK_DIV_W: .word 0x00000124
466 diff --git a/board/freescale/mx53_evk/mx53_evk.c b/board/freescale/mx53_evk/mx53_evk.c
468 index 0000000..1acfcc8
470 +++ b/board/freescale/mx53_evk/mx53_evk.c
473 + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
475 + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
477 + * See file CREDITS for list of people who contributed to this
480 + * This program is free software; you can redistribute it and/or
481 + * modify it under the terms of the GNU General Public License as
482 + * published by the Free Software Foundation; either version 2 of
483 + * the License, or (at your option) any later version.
485 + * This program is distributed in the hope that it will be useful,
486 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
487 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
488 + * GNU General Public License for more details.
490 + * You should have received a copy of the GNU General Public License
491 + * along with this program; if not, write to the Free Software
492 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
493 + * MA 02111-1307 USA
498 +#include <asm/arch/mx53.h>
499 +#include <asm/arch/mx53_pins.h>
500 +#include <asm/arch/iomux.h>
501 +#include <asm/errno.h>
502 +#include <imx_spi.h>
508 +#ifdef CONFIG_CMD_MMC
510 +#include <fsl_esdhc.h>
513 +DECLARE_GLOBAL_DATA_PTR;
515 +static u32 system_rev;
516 +static enum boot_device boot_dev;
517 +u32 mx51_io_base_addr;
519 +static inline void setup_boot_device(void)
521 + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
522 + uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
523 + uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
525 + switch (bt_mem_ctl) {
527 + boot_dev = MMC_BOOT;
530 + boot_dev = NAND_BOOT;
534 + boot_dev = SPI_NOR_BOOT;
537 + boot_dev = UNKNOWN_BOOT;
542 +enum boot_device get_boot_device(void)
547 +u32 get_board_rev(void)
552 +static inline void setup_soc_rev(void)
554 + system_rev = 0x53000 | CHIP_REV_1_0;
557 +static inline void set_board_rev(int rev)
559 + system_rev |= (rev & 0xF) << 8;
562 +inline int is_soc_rev(int rev)
564 + return (system_rev & 0xFF) - rev;
569 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
570 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
574 +static void setup_uart(void)
578 + mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
579 + mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 0x1E4);
580 + mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
583 + mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
584 + mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 0x1E4);
587 +#ifdef CONFIG_I2C_MXC
588 +static void setup_i2c(unsigned int module_base)
590 + switch (module_base) {
591 + case I2C1_BASE_ADDR:
593 + mxc_request_iomux(MX53_PIN_CSI0_D8,
594 + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
595 + mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
597 + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, PAD_CTL_SRE_FAST |
598 + PAD_CTL_ODE_OPENDRAIN_ENABLE |
599 + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
600 + PAD_CTL_HYS_ENABLE);
602 + mxc_request_iomux(MX53_PIN_CSI0_D9,
603 + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
604 + mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
606 + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, PAD_CTL_SRE_FAST |
607 + PAD_CTL_ODE_OPENDRAIN_ENABLE |
608 + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
609 + PAD_CTL_HYS_ENABLE);
611 + case I2C2_BASE_ADDR:
613 + mxc_request_iomux(MX53_PIN_KEY_ROW3,
614 + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
615 + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
617 + mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
619 + PAD_CTL_ODE_OPENDRAIN_ENABLE |
620 + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
621 + PAD_CTL_HYS_ENABLE);
624 + mxc_request_iomux(MX53_PIN_KEY_COL3,
625 + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
626 + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
628 + mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
630 + PAD_CTL_ODE_OPENDRAIN_ENABLE |
631 + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
632 + PAD_CTL_HYS_ENABLE);
635 + printf("Invalid I2C base: 0x%x\n", module_base);
640 +void setup_core_voltages(void)
642 + unsigned char buf[4] = { 0 };
644 + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
646 + /* Set core voltage VDDGP to 1.1V */
650 + if (i2c_write(0x8, 24, 1, buf, 3))
653 + /* Set DDR voltage VDDA to 1.225V */
657 + if (i2c_write(0x8, 26, 1, buf, 3))
660 + /* Raise the core frequency to 800MHz */
661 + writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
665 +void spi_io_init(struct imx_spi_dev_t *dev)
667 + switch (dev->base) {
668 + case CSPI1_BASE_ADDR:
669 + /* Select mux mode: ALT4 mux port: MOSI of instance: ecspi1 */
670 + mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4);
671 + mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0x104);
672 + mxc_iomux_set_input(
673 + MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, 0x3);
675 + /* Select mux mode: ALT4 mux port: MISO of instance: ecspi1. */
676 + mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4);
677 + mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0x104);
678 + mxc_iomux_set_input(
679 + MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT, 0x3);
681 + if (dev->ss == 0) {
682 + /* de-select SS1 of instance: ecspi1. */
683 + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
684 + mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x1E4);
686 + /* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */
687 + mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
688 + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x104);
689 + mxc_iomux_set_input(
690 + MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, 0x3);
691 + } else if (dev->ss == 1) {
692 + /* de-select SS0 of instance: ecspi1. */
693 + mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
694 + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x1E4);
696 + /* mux mode: ALT0 mux port: SS1 of instance: ecspi1. */
697 + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
698 + mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x104);
699 + mxc_iomux_set_input(
700 + MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, 0x2);
703 + /* Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
704 + mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4);
705 + mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0x104);
706 + mxc_iomux_set_input(
707 + MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x3);
710 + case CSPI2_BASE_ADDR:
717 +static void setup_fec(void)
719 + volatile unsigned int reg;
722 + mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
723 + mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, 0x1FC);
724 + mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1);
727 + mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
728 + mxc_iomux_set_pad(MX53_PIN_FEC_MDC, 0x004);
731 + mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
732 + mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, 0x180);
735 + mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
736 + mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, 0x180);
739 + mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
740 + mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, 0x004);
743 + mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
744 + mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, 0x004);
747 + mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
748 + mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, 0x004);
751 + mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
752 + mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, 0x180);
755 + mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
756 + mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, 0x180);
759 + mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
760 + mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, 0x180);
762 + /* phy reset: gpio7-6 */
763 + mxc_request_iomux(MX53_PIN_ATA_DA_0, IOMUX_CONFIG_ALT1);
765 + reg = readl(GPIO7_BASE_ADDR + 0x0);
767 + writel(reg, GPIO7_BASE_ADDR + 0x0);
769 + reg = readl(GPIO7_BASE_ADDR + 0x4);
771 + writel(reg, GPIO7_BASE_ADDR + 0x4);
775 + reg = readl(GPIO7_BASE_ADDR + 0x0);
777 + writel(reg, GPIO7_BASE_ADDR + 0x0);
781 +#ifdef CONFIG_CMD_MMC
783 +u32 *imx_esdhc_base_addr;
785 +int esdhc_gpio_init(void)
787 + u32 interface_esdhc = 0;
789 + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
791 + interface_esdhc = (soc_sbmr & (0x00300000)) >> 20;
793 + switch (interface_esdhc) {
795 + imx_esdhc_base_addr = (u32 *)MMC_SDHC1_BASE_ADDR;
797 + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
798 + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
799 + mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
800 + mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
801 + mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
802 + mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
804 + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
805 + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
806 + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
807 + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
808 + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
809 + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
812 + imx_esdhc_base_addr = (u32 *)MMC_SDHC3_BASE_ADDR;
814 + mxc_request_iomux(MX53_PIN_ATA_RESET_B, IOMUX_CONFIG_ALT2);
815 + mxc_request_iomux(MX53_PIN_ATA_IORDY, IOMUX_CONFIG_ALT2);
816 + mxc_request_iomux(MX53_PIN_ATA_DATA8, IOMUX_CONFIG_ALT4);
817 + mxc_request_iomux(MX53_PIN_ATA_DATA9, IOMUX_CONFIG_ALT4);
818 + mxc_request_iomux(MX53_PIN_ATA_DATA10, IOMUX_CONFIG_ALT4);
819 + mxc_request_iomux(MX53_PIN_ATA_DATA11, IOMUX_CONFIG_ALT4);
820 + mxc_request_iomux(MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT4);
821 + mxc_request_iomux(MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT4);
822 + mxc_request_iomux(MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT4);
823 + mxc_request_iomux(MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT4);
825 + mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 0x1E4);
826 + mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 0xD4);
827 + mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 0x1D4);
828 + mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 0x1D4);
829 + mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 0x1D4);
830 + mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 0x1D4);
831 + mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 0x1D4);
832 + mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4);
833 + mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4);
834 + mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4);
845 +int board_mmc_init(void)
847 + if (!esdhc_gpio_init())
848 + return fsl_esdhc_mmc_init(gd->bd);
855 +int board_init(void)
857 + setup_boot_device();
860 + gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK; /* board id for linux */
861 + /* address of boot parameters */
862 + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
867 +#ifdef CONFIG_I2C_MXC
868 + setup_i2c(CONFIG_SYS_I2C_PORT);
869 + setup_core_voltages();
875 +int board_late_init(void)
880 +int checkboard(void)
882 + printf("Board: MX53 EVK ");
887 + switch (__REG(SRC_BASE_ADDR + 0x8)) {
903 + printf("Boot Device: ");
904 + switch (get_boot_device()) {
909 + printf("SPI NOR\n");
916 + printf("UNKNOWN\n");
921 diff --git a/board/freescale/mx53_evk/u-boot.lds b/board/freescale/mx53_evk/u-boot.lds
923 index 0000000..fe5f4eb
925 +++ b/board/freescale/mx53_evk/u-boot.lds
928 + * January 2004 - Changed to support H4 device
929 + * Copyright (c) 2004 Texas Instruments
931 + * (C) Copyright 2002
932 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
934 + * (C) Copyright 2010 Freescale Semiconductor, Inc.
936 + * See file CREDITS for list of people who contributed to this
939 + * This program is free software; you can redistribute it and/or
940 + * modify it under the terms of the GNU General Public License as
941 + * published by the Free Software Foundation; either version 2 of
942 + * the License, or (at your option) any later version.
944 + * This program is distributed in the hope that it will be useful,
945 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
946 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
947 + * GNU General Public License for more details.
949 + * You should have received a copy of the GNU General Public License
950 + * along with this program; if not, write to the Free Software
951 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
952 + * MA 02111-1307 USA
955 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
965 + /* WARNING - the following is hand-optimized to fit within */
966 + /* the sector layout of our flash chips! XXX FIXME XXX */
967 + board/freescale/mx53_evk/flash_header.o (.text.flasheader)
968 + cpu/arm_cortexa8/start.o
969 + board/freescale/mx53_evk/libmx53_evk.a (.text)
970 + lib_arm/libarm.a (.text)
971 + net/libnet.a (.text)
972 + drivers/mtd/libmtd.a (.text)
973 + drivers/mmc/libmmc.a (.text)
975 + . = DEFINED(env_offset) ? env_offset : .;
976 + common/env_embedded.o(.text)
982 + .rodata : { *(.rodata) }
985 + .data : { *(.data) }
991 + __u_boot_cmd_start = .;
992 + .u_boot_cmd : { *(.u_boot_cmd) }
993 + __u_boot_cmd_end = .;
1000 diff --git a/cpu/arm_cortexa8/Makefile b/cpu/arm_cortexa8/Makefile
1001 index ae20299..b8efc4e 100644
1002 --- a/cpu/arm_cortexa8/Makefile
1003 +++ b/cpu/arm_cortexa8/Makefile
1004 @@ -44,4 +44,4 @@ include $(SRCTREE)/rules.mk
1006 sinclude $(obj).depend
1008 -#########################################################################
1009 \ No newline at end of file
1010 +#########################################################################
1011 diff --git a/cpu/arm_cortexa8/mx53/Makefile b/cpu/arm_cortexa8/mx53/Makefile
1012 new file mode 100644
1013 index 0000000..460bdd9
1015 +++ b/cpu/arm_cortexa8/mx53/Makefile
1018 +# (C) Copyright 2000-2006
1019 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1021 +# (C) Copyright 2010 Freescale Semiconductor, Inc.
1023 +# See file CREDITS for list of people who contributed to this
1026 +# This program is free software; you can redistribute it and/or
1027 +# modify it under the terms of the GNU General Public License as
1028 +# published by the Free Software Foundation; either version 2 of
1029 +# the License, or (at your option) any later version.
1031 +# This program is distributed in the hope that it will be useful,
1032 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
1033 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1034 +# GNU General Public License for more details.
1036 +# You should have received a copy of the GNU General Public License
1037 +# along with this program; if not, write to the Free Software
1038 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1039 +# MA 02111-1307 USA
1042 +include $(TOPDIR)/config.mk
1044 +LIB = $(obj)lib$(SOC).a
1046 +COBJS = interrupts.o serial.o generic.o iomux.o timer.o cache.o
1047 +COBJS += $(COBJS-y)
1049 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
1050 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
1052 +all: $(obj).depend $(LIB)
1055 + $(AR) $(ARFLAGS) $@ $(OBJS)
1057 +#########################################################################
1059 +# defines $(obj).depend target
1060 +include $(SRCTREE)/rules.mk
1062 +sinclude $(obj).depend
1064 +#########################################################################
1065 diff --git a/cpu/arm_cortexa8/mx53/cache.c b/cpu/arm_cortexa8/mx53/cache.c
1066 new file mode 100755
1067 index 0000000..60df92f
1069 +++ b/cpu/arm_cortexa8/mx53/cache.c
1072 + * Copyright (C) 2010 Freescale Semiconductor, Inc.
1074 + * See file CREDITS for list of people who contributed to this
1077 + * This program is free software; you can redistribute it and/or
1078 + * modify it under the terms of the GNU General Public License as
1079 + * published by the Free Software Foundation; either version 2 of
1080 + * the License, or (at your option) any later version.
1082 + * This program is distributed in the hope that it will be useful,
1083 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1084 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1085 + * GNU General Public License for more details.
1087 + * You should have received a copy of the GNU General Public License
1088 + * along with this program; if not, write to the Free Software
1089 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1090 + * MA 02111-1307 USA
1093 +#include <common.h>
1094 +#include <asm/cache.h>
1096 +void l2_cache_enable(void)
1098 + asm("mrc 15, 0, r0, c1, c0, 1");
1099 + asm("orr r0, r0, #0x2");
1100 + asm("mcr 15, 0, r0, c1, c0, 1");
1103 +void l2_cache_disable(void)
1105 + asm("mrc 15, 0, r0, c1, c0, 1");
1106 + asm("bic r0, r0, #0x2");
1107 + asm("mcr 15, 0, r0, c1, c0, 1");
1110 +/*dummy function for L2 ON*/
1111 +u32 get_device_type(void)
1115 diff --git a/cpu/arm_cortexa8/mx53/crm_regs.h b/cpu/arm_cortexa8/mx53/crm_regs.h
1116 new file mode 100644
1117 index 0000000..92a083e
1119 +++ b/cpu/arm_cortexa8/mx53/crm_regs.h
1122 + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
1124 + * This program is free software; you can redistribute it and/or modify
1125 + * it under the terms of the GNU General Public License as published by
1126 + * the Free Software Foundation; either version 2 of the License, or
1127 + * (at your option) any later version.
1129 + * This program is distributed in the hope that it will be useful,
1130 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1131 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1132 + * GNU General Public License for more details.
1134 + * You should have received a copy of the GNU General Public License along
1135 + * with this program; if not, write to the Free Software Foundation, Inc.,
1136 + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
1139 +#ifndef __ARCH_ARM_MACH_MX53_CRM_REGS_H__
1140 +#define __ARCH_ARM_MACH_MX53_CRM_REGS_H__
1142 +#define MXC_CCM_BASE CCM_BASE_ADDR
1143 +#define MXC_DPLL1_BASE PLL1_BASE_ADDR
1144 +#define MXC_DPLL2_BASE PLL2_BASE_ADDR
1145 +#define MXC_DPLL3_BASE PLL3_BASE_ADDR
1146 +#define MXC_DPLL4_BASE PLL4_BASE_ADDR
1148 +/* PLL Register Offsets */
1149 +#define MXC_PLL_DP_CTL 0x00
1150 +#define MXC_PLL_DP_CONFIG 0x04
1151 +#define MXC_PLL_DP_OP 0x08
1152 +#define MXC_PLL_DP_MFD 0x0C
1153 +#define MXC_PLL_DP_MFN 0x10
1154 +#define MXC_PLL_DP_MFNMINUS 0x14
1155 +#define MXC_PLL_DP_MFNPLUS 0x18
1156 +#define MXC_PLL_DP_HFS_OP 0x1C
1157 +#define MXC_PLL_DP_HFS_MFD 0x20
1158 +#define MXC_PLL_DP_HFS_MFN 0x24
1159 +#define MXC_PLL_DP_MFN_TOGC 0x28
1160 +#define MXC_PLL_DP_DESTAT 0x2c
1162 +/* PLL Register Bit definitions */
1163 +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
1164 +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
1165 +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
1166 +#define MXC_PLL_DP_CTL_ADE 0x800
1167 +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
1168 +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
1169 +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
1170 +#define MXC_PLL_DP_CTL_HFSM 0x80
1171 +#define MXC_PLL_DP_CTL_PRE 0x40
1172 +#define MXC_PLL_DP_CTL_UPEN 0x20
1173 +#define MXC_PLL_DP_CTL_RST 0x10
1174 +#define MXC_PLL_DP_CTL_RCP 0x8
1175 +#define MXC_PLL_DP_CTL_PLM 0x4
1176 +#define MXC_PLL_DP_CTL_BRM0 0x2
1177 +#define MXC_PLL_DP_CTL_LRF 0x1
1179 +#define MXC_PLL_DP_CONFIG_BIST 0x8
1180 +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
1181 +#define MXC_PLL_DP_CONFIG_AREN 0x2
1182 +#define MXC_PLL_DP_CONFIG_LDREQ 0x1
1184 +#define MXC_PLL_DP_OP_MFI_OFFSET 4
1185 +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
1186 +#define MXC_PLL_DP_OP_PDF_OFFSET 0
1187 +#define MXC_PLL_DP_OP_PDF_MASK 0xF
1189 +#define MXC_PLL_DP_MFD_OFFSET 0
1190 +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
1192 +#define MXC_PLL_DP_MFN_OFFSET 0x0
1193 +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
1195 +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
1196 +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
1197 +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
1198 +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
1200 +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
1201 +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
1203 +/* Register addresses of CCM*/
1204 +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
1205 +#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
1206 +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
1207 +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
1208 +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
1209 +#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
1210 +#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
1211 +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
1212 +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
1213 +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
1214 +#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
1215 +#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
1216 +#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
1217 +#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
1218 +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
1219 +#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
1220 +#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
1221 +#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
1222 +#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
1223 +#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
1224 +#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
1225 +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
1226 +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
1227 +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
1228 +#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
1229 +#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
1230 +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
1231 +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
1232 +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
1233 +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
1234 +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
1235 +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
1236 +#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
1237 +#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x80)
1238 +#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88)
1240 +/* Define the bits in register CCR */
1241 +#define MXC_CCM_CCR_COSC_EN (1 << 12)
1242 +#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
1243 +#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
1244 +#define MXC_CCM_CCR_FPM_EN (1 << 8)
1245 +#define MXC_CCM_CCR_OSCNT_OFFSET (0)
1246 +#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
1248 +/* Define the bits in register CCDR */
1249 +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 21)
1250 +#define MXC_CCM_CCDR_EMI_HS_INT2_MASK (0x1 << 20)
1251 +#define MXC_CCM_CCDR_EMI_HS_INT1_MASK (0x1 << 19)
1252 +#define MXC_CCM_CCDR_EMI_HS_SLOW_MASK (0x1 << 18)
1253 +#define MXC_CCM_CCDR_EMI_HS_FAST_MASK (0x1 << 17)
1254 +#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
1256 +/* Define the bits in register CSR */
1257 +#define MXC_CCM_CSR_COSR_READY (1 << 5)
1258 +#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
1259 +#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
1260 +#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
1261 +#define MXC_CCM_CSR_TEMP_MON_ALARM (1 << 1)
1262 +#define MXC_CCM_CSR_REF_EN_B (1 << 0)
1264 +/* Define the bits in register CCSR */
1265 +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 10)
1266 +#define MXC_CCM_CCSR_LP_APM_SEL_OFFSET 10
1267 +#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (1 << 9)
1268 +#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
1269 +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
1270 +#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
1271 +#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
1272 +#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
1273 +#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
1274 +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
1275 +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
1276 +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
1278 +/* Define the bits in register CACRR */
1279 +#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
1280 +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
1282 +/* Define the bits in register CBCDR */
1283 +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
1284 +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
1285 +#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
1286 +#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
1287 +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
1288 +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
1289 +#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
1290 +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
1291 +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
1292 +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
1293 +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
1294 +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
1295 +#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
1296 +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
1297 +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
1298 +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
1299 +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
1300 +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
1301 +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
1302 +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
1303 +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
1304 +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
1305 +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
1306 +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
1308 +/* Define the bits in register CBCMR */
1309 +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16)
1310 +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
1311 +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
1312 +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
1313 +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
1314 +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
1315 +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
1316 +#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
1317 +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
1318 +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
1319 +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
1320 +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
1321 +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
1322 +#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
1323 +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
1324 +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
1326 +/* Define the bits in register CSCMR1 */
1327 +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
1328 +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
1329 +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
1330 +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
1331 +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
1332 +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
1333 +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
1334 +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
1335 +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
1336 +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
1337 +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
1338 +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
1339 +#define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 19)
1340 +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
1341 +#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET (16)
1342 +#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK (0x3 << 16)
1343 +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
1344 +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
1345 +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
1346 +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
1347 +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
1348 +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
1349 +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
1350 +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
1351 +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
1352 +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
1353 +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
1354 +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
1355 +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
1356 +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
1357 +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
1359 +/* Define the bits in register CSCMR2 */
1360 +#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
1361 +#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
1362 +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
1363 +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
1364 +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
1365 +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
1366 +#define MXC_CCM_CSCMR2_ASRC_CLK_SEL (1<<21)
1367 +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET (19)
1368 +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
1369 +#define MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET (16)
1370 +#define MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK (0x7 << 16)
1371 +#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_OFFSET (14)
1372 +#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_MASK (0x3 << 14)
1373 +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
1374 +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
1375 +#define MXC_CCM_CSCMR2_LBD_DI1_IPU_DIV (0x1 << 11)
1376 +#define MXC_CCM_CSCMR2_LBD_DI0_IPU_DIV (0x1 << 10)
1377 +#define MXC_CCM_CSCMR2_LBD_DI1_CLK_SEL (0x1 << 9)
1378 +#define MXC_CCM_CSCMR2_LBD_DI0_CLK_SEL (0x1 << 8)
1379 +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (6)
1380 +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 6)
1381 +#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
1382 +#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
1383 +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
1384 +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
1385 +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
1386 +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
1388 +/* Define the bits in register CSCDR1 */
1389 +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET (22)
1390 +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK (0x7 << 22)
1391 +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET (19)
1392 +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK (0x7 << 19)
1393 +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
1394 +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
1395 +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
1396 +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
1397 +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
1398 +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
1399 +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
1400 +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
1401 +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
1402 +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
1403 +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
1404 +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
1405 +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
1406 +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
1408 +/* Define the bits in register CS1CDR and CS2CDR */
1409 +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET (25)
1410 +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
1411 +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
1412 +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
1413 +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
1414 +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
1415 +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET (9)
1416 +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x7 << 9)
1417 +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
1418 +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
1419 +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
1420 +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
1422 +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
1423 +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
1424 +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
1425 +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
1426 +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
1427 +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
1428 +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
1429 +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
1431 +/* Define the bits in register CDCDR */
1432 +#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
1433 +#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
1434 +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
1435 +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
1436 +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
1437 +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
1438 +#define MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET (16)
1439 +#define MXC_CCM_CDCDR_DI_PLL4_PODF_MASK (0x7 << 16)
1440 +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
1441 +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
1442 +#define MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET (6)
1443 +#define MXC_CCM_CDCDR_DI1_CLK_PRED_MASK (0x7 << 6)
1444 +#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
1445 +#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
1446 +#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
1447 +#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
1449 +/* Define the bits in register CHSCCDR */
1450 +#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_OFFSET (6)
1451 +#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_MASK (0x3 << 6)
1452 +#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_OFFSET (4)
1453 +#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_MASK (0x3 << 4)
1454 +#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_OFFSET (2)
1455 +#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_MASK (0x3 << 2)
1456 +#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_OFFSET (0)
1457 +#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_MASK (0x3)
1459 +/* Define the bits in register CSCDR2 */
1460 +#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET (28)
1461 +#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK (0x7 << 28)
1462 +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
1463 +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
1464 +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
1465 +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
1466 +#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET (9)
1467 +#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK (0x3F << 9)
1468 +#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET (6)
1469 +#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK (0x7 << 6)
1470 +#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET (0)
1471 +#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK (0x3F)
1473 +/* Define the bits in register CSCDR3 */
1474 +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
1475 +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
1476 +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
1477 +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
1478 +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
1479 +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
1480 +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
1481 +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
1483 +/* Define the bits in register CSCDR4 */
1484 +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
1485 +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
1486 +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
1487 +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
1488 +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
1489 +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
1490 +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
1491 +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
1493 +/* Define the bits in register CDHIPR */
1494 +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
1495 +#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
1496 +#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
1497 +#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
1498 +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
1499 +#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
1500 +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
1501 +#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
1502 +#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
1503 +#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
1505 +/* Define the bits in register CDCR */
1506 +#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
1507 +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
1508 +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
1510 +/* Define the bits in register CLPCR */
1511 +#define MXC_CCM_CLPCR_BYPASS_CAN2_LPM_HS (0x1 << 27)
1512 +#define MXC_CCM_CLPCR_BYPASS_CAN1_LPM_HS (0x1 << 27)
1513 +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 26)
1514 +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
1515 +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 24)
1516 +#define MXC_CCM_CLPCR_BYPASS_EMI_INT2_LPM_HS (0x1 << 23)
1517 +#define MXC_CCM_CLPCR_BYPASS_EMI_INT1_LPM_HS (0x1 << 22)
1518 +#define MXC_CCM_CLPCR_BYPASS_EMI_SLOW_LPM_HS (0x1 << 21)
1519 +#define MXC_CCM_CLPCR_BYPASS_EMI_FAST_LPM_HS (0x1 << 20)
1520 +#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
1521 +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
1522 +#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
1523 +#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
1524 +#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
1525 +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
1526 +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
1527 +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
1528 +#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
1529 +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
1530 +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
1531 +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
1532 +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
1533 +#define MXC_CCM_CLPCR_LPM_OFFSET (0)
1534 +#define MXC_CCM_CLPCR_LPM_MASK (0x3)
1536 +/* Define the bits in register CISR */
1537 +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 26)
1538 +#define MXC_CCM_CISR_TEMP_MON_ALARM (0x1 << 25)
1539 +#define MXC_CCM_CISR_EMI_CLK_SEL_LOADED (0x1 << 23)
1540 +#define MXC_CCM_CISR_PER_CLK_SEL_LOADED (0x1 << 22)
1541 +#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
1542 +#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
1543 +#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
1544 +#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
1545 +#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
1546 +#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
1547 +#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
1548 +#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
1549 +#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
1550 +#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
1551 +#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
1552 +#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
1553 +#define MXC_CCM_CISR_LRF_PLL1 (0x1)
1555 +/* Define the bits in register CIMR */
1556 +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 26)
1557 +#define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM (0x1 << 25)
1558 +#define MXC_CCM_CIMR_MASK_EMI_CLK_SEL_LOADED (0x1 << 23)
1559 +#define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED (0x1 << 22)
1560 +#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
1561 +#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (0x1 << 20)
1562 +#define MXC_CCM_CIMR_MASK_EMI_SLOW_PODF_LOADED (0x1 << 19)
1563 +#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
1564 +#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
1565 +#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
1566 +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 6)
1567 +#define MXC_CCM_CIMR_MASK_CAMP2_READY (0x1 << 5)
1568 +#define MXC_CCM_CIMR_MASK_CAMP1_READY (0x1 << 4)
1569 +#define MXC_CCM_CIMR_MASK_LRF_PLL4 (0x1 << 3)
1570 +#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
1571 +#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
1572 +#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
1574 +/* Define the bits in register CCOSR */
1575 +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
1576 +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
1577 +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
1578 +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
1579 +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
1580 +#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
1581 +#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
1582 +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
1583 +#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
1584 +#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
1586 +/* Define the bits in registers CGPR */
1587 +#define MXC_CCM_CGPR_ARM_CLK_INPUT_SEL (0x1 << 24)
1588 +#define MXC_CCM_CGPR_ARM_ASYNC_REF_EN (0x1 << 23)
1589 +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
1590 +#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
1591 +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
1592 +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
1594 +/* Define the bits in registers CCGRx */
1595 +#define MXC_CCM_CCGR_CG_MASK 0x3
1597 +#define MXC_CCM_CCGR0_CG15_OFFSET 30
1598 +#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
1599 +#define MXC_CCM_CCGR0_CG14_OFFSET 28
1600 +#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
1601 +#define MXC_CCM_CCGR0_CG13_OFFSET 26
1602 +#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
1603 +#define MXC_CCM_CCGR0_CG12_OFFSET 24
1604 +#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
1605 +#define MXC_CCM_CCGR0_CG11_OFFSET 22
1606 +#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
1607 +#define MXC_CCM_CCGR0_CG10_OFFSET 20
1608 +#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
1609 +#define MXC_CCM_CCGR0_CG9_OFFSET 18
1610 +#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
1611 +#define MXC_CCM_CCGR0_CG8_OFFSET 16
1612 +#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
1613 +#define MXC_CCM_CCGR0_CG7_OFFSET 14
1614 +#define MXC_CCM_CCGR0_CG6_OFFSET 12
1615 +#define MXC_CCM_CCGR0_CG5_OFFSET 10
1616 +#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
1617 +#define MXC_CCM_CCGR0_CG4_OFFSET 8
1618 +#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
1619 +#define MXC_CCM_CCGR0_CG3_OFFSET 6
1620 +#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
1621 +#define MXC_CCM_CCGR0_CG2_OFFSET 4
1622 +#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
1623 +#define MXC_CCM_CCGR0_CG1_OFFSET 2
1624 +#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
1625 +#define MXC_CCM_CCGR0_CG0_OFFSET 0
1626 +#define MXC_CCM_CCGR0_CG0_MASK 0x3
1628 +#define MXC_CCM_CCGR1_CG15_OFFSET 30
1629 +#define MXC_CCM_CCGR1_CG14_OFFSET 28
1630 +#define MXC_CCM_CCGR1_CG13_OFFSET 26
1631 +#define MXC_CCM_CCGR1_CG12_OFFSET 24
1632 +#define MXC_CCM_CCGR1_CG11_OFFSET 22
1633 +#define MXC_CCM_CCGR1_CG10_OFFSET 20
1634 +#define MXC_CCM_CCGR1_CG9_OFFSET 18
1635 +#define MXC_CCM_CCGR1_CG8_OFFSET 16
1636 +#define MXC_CCM_CCGR1_CG7_OFFSET 14
1637 +#define MXC_CCM_CCGR1_CG6_OFFSET 12
1638 +#define MXC_CCM_CCGR1_CG5_OFFSET 10
1639 +#define MXC_CCM_CCGR1_CG4_OFFSET 8
1640 +#define MXC_CCM_CCGR1_CG3_OFFSET 6
1641 +#define MXC_CCM_CCGR1_CG2_OFFSET 4
1642 +#define MXC_CCM_CCGR1_CG1_OFFSET 2
1643 +#define MXC_CCM_CCGR1_CG0_OFFSET 0
1645 +#define MXC_CCM_CCGR2_CG15_OFFSET 30
1646 +#define MXC_CCM_CCGR2_CG14_OFFSET 28
1647 +#define MXC_CCM_CCGR2_CG13_OFFSET 26
1648 +#define MXC_CCM_CCGR2_CG12_OFFSET 24
1649 +#define MXC_CCM_CCGR2_CG11_OFFSET 22
1650 +#define MXC_CCM_CCGR2_CG10_OFFSET 20
1651 +#define MXC_CCM_CCGR2_CG9_OFFSET 18
1652 +#define MXC_CCM_CCGR2_CG8_OFFSET 16
1653 +#define MXC_CCM_CCGR2_CG7_OFFSET 14
1654 +#define MXC_CCM_CCGR2_CG6_OFFSET 12
1655 +#define MXC_CCM_CCGR2_CG5_OFFSET 10
1656 +#define MXC_CCM_CCGR2_CG4_OFFSET 8
1657 +#define MXC_CCM_CCGR2_CG3_OFFSET 6
1658 +#define MXC_CCM_CCGR2_CG2_OFFSET 4
1659 +#define MXC_CCM_CCGR2_CG1_OFFSET 2
1660 +#define MXC_CCM_CCGR2_CG0_OFFSET 0
1662 +#define MXC_CCM_CCGR3_CG15_OFFSET 30
1663 +#define MXC_CCM_CCGR3_CG14_OFFSET 28
1664 +#define MXC_CCM_CCGR3_CG13_OFFSET 26
1665 +#define MXC_CCM_CCGR3_CG12_OFFSET 24
1666 +#define MXC_CCM_CCGR3_CG11_OFFSET 22
1667 +#define MXC_CCM_CCGR3_CG10_OFFSET 20
1668 +#define MXC_CCM_CCGR3_CG9_OFFSET 18
1669 +#define MXC_CCM_CCGR3_CG8_OFFSET 16
1670 +#define MXC_CCM_CCGR3_CG7_OFFSET 14
1671 +#define MXC_CCM_CCGR3_CG6_OFFSET 12
1672 +#define MXC_CCM_CCGR3_CG5_OFFSET 10
1673 +#define MXC_CCM_CCGR3_CG4_OFFSET 8
1674 +#define MXC_CCM_CCGR3_CG3_OFFSET 6
1675 +#define MXC_CCM_CCGR3_CG2_OFFSET 4
1676 +#define MXC_CCM_CCGR3_CG1_OFFSET 2
1677 +#define MXC_CCM_CCGR3_CG0_OFFSET 0
1679 +#define MXC_CCM_CCGR4_CG15_OFFSET 30
1680 +#define MXC_CCM_CCGR4_CG14_OFFSET 28
1681 +#define MXC_CCM_CCGR4_CG13_OFFSET 26
1682 +#define MXC_CCM_CCGR4_CG12_OFFSET 24
1683 +#define MXC_CCM_CCGR4_CG11_OFFSET 22
1684 +#define MXC_CCM_CCGR4_CG10_OFFSET 20
1685 +#define MXC_CCM_CCGR4_CG9_OFFSET 18
1686 +#define MXC_CCM_CCGR4_CG8_OFFSET 16
1687 +#define MXC_CCM_CCGR4_CG7_OFFSET 14
1688 +#define MXC_CCM_CCGR4_CG6_OFFSET 12
1689 +#define MXC_CCM_CCGR4_CG5_OFFSET 10
1690 +#define MXC_CCM_CCGR4_CG4_OFFSET 8
1691 +#define MXC_CCM_CCGR4_CG3_OFFSET 6
1692 +#define MXC_CCM_CCGR4_CG2_OFFSET 4
1693 +#define MXC_CCM_CCGR4_CG1_OFFSET 2
1694 +#define MXC_CCM_CCGR4_CG0_OFFSET 0
1696 +#define MXC_CCM_CCGR5_CG15_OFFSET 30
1697 +#define MXC_CCM_CCGR5_CG14_OFFSET 28
1698 +#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
1699 +#define MXC_CCM_CCGR5_CG13_OFFSET 26
1700 +#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
1701 +#define MXC_CCM_CCGR5_CG12_OFFSET 24
1702 +#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
1703 +#define MXC_CCM_CCGR5_CG11_OFFSET 22
1704 +#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
1705 +#define MXC_CCM_CCGR5_CG10_OFFSET 20
1706 +#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
1707 +#define MXC_CCM_CCGR5_CG9_OFFSET 18
1708 +#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
1709 +#define MXC_CCM_CCGR5_CG8_OFFSET 16
1710 +#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
1711 +#define MXC_CCM_CCGR5_CG7_OFFSET 14
1712 +#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
1713 +#define MXC_CCM_CCGR5_CG6_OFFSET 12
1714 +#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
1715 +#define MXC_CCM_CCGR5_CG5_OFFSET 10
1716 +#define MXC_CCM_CCGR5_CG4_OFFSET 8
1717 +#define MXC_CCM_CCGR5_CG3_OFFSET 6
1718 +#define MXC_CCM_CCGR5_CG2_OFFSET 4
1719 +#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
1720 +#define MXC_CCM_CCGR5_CG1_OFFSET 2
1721 +#define MXC_CCM_CCGR5_CG0_OFFSET 0
1723 +#define MXC_CCM_CCGR6_CG15_OFFSET 30
1724 +#define MXC_CCM_CCGR6_CG14_OFFSET 28
1725 +#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
1726 +#define MXC_CCM_CCGR6_CG13_OFFSET 26
1727 +#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
1728 +#define MXC_CCM_CCGR6_CG12_OFFSET 24
1729 +#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
1730 +#define MXC_CCM_CCGR6_CG11_OFFSET 22
1731 +#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
1732 +#define MXC_CCM_CCGR6_CG10_OFFSET 20
1733 +#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
1734 +#define MXC_CCM_CCGR6_CG9_OFFSET 18
1735 +#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
1736 +#define MXC_CCM_CCGR6_CG8_OFFSET 16
1737 +#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
1738 +#define MXC_CCM_CCGR6_CG7_OFFSET 14
1739 +#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
1740 +#define MXC_CCM_CCGR6_CG6_OFFSET 12
1741 +#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
1742 +#define MXC_CCM_CCGR6_CG5_OFFSET 10
1743 +#define MXC_CCM_CCGR6_CG4_OFFSET 8
1744 +#define MXC_CCM_CCGR6_CG3_OFFSET 6
1745 +#define MXC_CCM_CCGR6_CG2_OFFSET 4
1746 +#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
1747 +#define MXC_CCM_CCGR6_CG1_OFFSET 2
1748 +#define MXC_CCM_CCGR6_CG0_OFFSET 0
1750 +#define MXC_CCM_CCGR7_CG15_OFFSET 30
1751 +#define MXC_CCM_CCGR7_CG14_OFFSET 28
1752 +#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
1753 +#define MXC_CCM_CCGR7_CG13_OFFSET 26
1754 +#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
1755 +#define MXC_CCM_CCGR7_CG12_OFFSET 24
1756 +#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
1757 +#define MXC_CCM_CCGR7_CG11_OFFSET 22
1758 +#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
1759 +#define MXC_CCM_CCGR7_CG10_OFFSET 20
1760 +#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
1761 +#define MXC_CCM_CCGR7_CG9_OFFSET 18
1762 +#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
1763 +#define MXC_CCM_CCGR7_CG8_OFFSET 16
1764 +#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
1765 +#define MXC_CCM_CCGR7_CG7_OFFSET 14
1766 +#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
1767 +#define MXC_CCM_CCGR7_CG6_OFFSET 12
1768 +#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
1769 +#define MXC_CCM_CCGR7_CG5_OFFSET 10
1770 +#define MXC_CCM_CCGR7_CG4_OFFSET 8
1771 +#define MXC_CCM_CCGR7_CG3_OFFSET 6
1772 +#define MXC_CCM_CCGR7_CG2_OFFSET 4
1773 +#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
1774 +#define MXC_CCM_CCGR7_CG1_OFFSET 2
1775 +#define MXC_CCM_CCGR7_CG0_OFFSET 0
1777 +#define MXC_GPC_BASE (IO_ADDRESS(GPC_BASE_ADDR))
1778 +#define MXC_DPTC_LP_BASE (MXC_GPC_BASE + 0x80)
1779 +#define MXC_DPTC_GP_BASE (MXC_GPC_BASE + 0x100)
1780 +#define MXC_DVFS_CORE_BASE (MXC_GPC_BASE + 0x180)
1781 +#define MXC_DVFS_PER_BASE (MXC_GPC_BASE + 0x1C4)
1782 +#define MXC_PGC_IPU_BASE (MXC_GPC_BASE + 0x220)
1783 +#define MXC_PGC_VPU_BASE (MXC_GPC_BASE + 0x240)
1784 +#define MXC_PGC_GPU_BASE (MXC_GPC_BASE + 0x260)
1785 +#define MXC_SRPG_NEON_BASE (MXC_GPC_BASE + 0x280)
1786 +#define MXC_SRPG_ARM_BASE (MXC_GPC_BASE + 0x2A0)
1787 +#define MXC_SRPG_EMPGC0_BASE (MXC_GPC_BASE + 0x2C0)
1788 +#define MXC_SRPG_EMPGC1_BASE (MXC_GPC_BASE + 0x2D0)
1789 +#define MXC_SRPG_MEGAMIX_BASE (MXC_GPC_BASE + 0x2E0)
1790 +#define MXC_SRPG_EMI_BASE (MXC_GPC_BASE + 0x300)
1793 +#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
1794 +#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
1795 +#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
1796 +#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
1797 +#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
1798 +#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
1799 +#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
1800 +#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
1801 +#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
1802 +#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
1803 +#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
1804 +#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
1805 +#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
1806 +#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
1807 +#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
1808 +#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
1809 +#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
1812 +#define MXC_DVFSPER_LTR0 (MXC_DVFS_PER_BASE)
1813 +#define MXC_DVFSPER_LTR1 (MXC_DVFS_PER_BASE + 0x04)
1814 +#define MXC_DVFSPER_LTR2 (MXC_DVFS_PER_BASE + 0x08)
1815 +#define MXC_DVFSPER_LTR3 (MXC_DVFS_PER_BASE + 0x0C)
1816 +#define MXC_DVFSPER_LTBR0 (MXC_DVFS_PER_BASE + 0x10)
1817 +#define MXC_DVFSPER_LTBR1 (MXC_DVFS_PER_BASE + 0x14)
1818 +#define MXC_DVFSPER_PMCR0 (MXC_DVFS_PER_BASE + 0x18)
1819 +#define MXC_DVFSPER_PMCR1 (MXC_DVFS_PER_BASE + 0x1C)
1822 +#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
1823 +#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
1824 +#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
1825 +#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC)
1826 +#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10)
1829 +#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
1830 +#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
1831 +#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
1832 +#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
1833 +#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
1834 +#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
1836 +#define MXC_PGCR_PCR 1
1837 +#define MXC_SRPGCR_PCR 1
1838 +#define MXC_EMPGCR_PCR 1
1839 +#define MXC_PGSR_PSR 1
1842 +#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
1843 +#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
1846 +#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
1847 +#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
1848 +#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
1850 +#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
1851 +#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
1852 +#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
1854 +#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
1855 +#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
1856 +#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
1858 +#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
1859 +#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
1860 +#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
1862 +#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
1863 +#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
1864 +#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
1866 +#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
1867 +#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
1868 +#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
1870 +#endif /* __ARCH_ARM_MACH_MX53_CRM_REGS_H__ */
1871 diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c
1872 new file mode 100644
1873 index 0000000..01220c3
1875 +++ b/cpu/arm_cortexa8/mx53/generic.c
1878 + * Copyright (C) 2010 Freescale Semiconductor, Inc.
1880 + * See file CREDITS for list of people who contributed to this
1883 + * This program is free software; you can redistribute it and/or
1884 + * modify it under the terms of the GNU General Public License as
1885 + * published by the Free Software Foundation; either version 2 of
1886 + * the License, or (at your option) any later version.
1888 + * This program is distributed in the hope that it will be useful,
1889 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1890 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1891 + * GNU General Public License for more details.
1893 + * You should have received a copy of the GNU General Public License
1894 + * along with this program; if not, write to the Free Software
1895 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1896 + * MA 02111-1307 USA
1899 +#include <common.h>
1900 +#include <asm/arch/mx53.h>
1901 +#include <asm/errno.h>
1902 +#include "crm_regs.h"
1905 + PLL1_CLK = MXC_DPLL1_BASE,
1906 + PLL2_CLK = MXC_DPLL2_BASE,
1907 + PLL3_CLK = MXC_DPLL3_BASE,
1908 + PLL4_CLK = MXC_DPLL4_BASE,
1911 +enum pll_sw_clocks {
1918 +static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
1920 + u32 mfi, mfn, mfd, pd;
1922 + mfn = __REG(pll + MXC_PLL_DP_MFN);
1923 + mfd = __REG(pll + MXC_PLL_DP_MFD) + 1;
1924 + mfi = __REG(pll + MXC_PLL_DP_OP);
1925 + pd = (mfi & 0xF) + 1;
1926 + mfi = (mfi >> 4) & 0xF;
1927 + mfi = (mfi >= 5) ? mfi : 5;
1929 + return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
1932 +static u32 __get_mcu_main_clk(void)
1935 + reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
1936 + MXC_CCM_CACRR_ARM_PODF_OFFSET;
1937 + freq = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ);
1938 + return freq / (reg + 1);
1941 +static u32 __get_periph_clk(void)
1944 + reg = __REG(MXC_CCM_CBCDR);
1945 + if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
1946 + reg = __REG(MXC_CCM_CBCMR);
1947 + switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
1948 + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
1950 + return __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ);
1952 + return __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ);
1957 + return __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ);
1960 +static u32 __get_ipg_clk(void)
1962 + u32 ahb_podf, ipg_podf;
1964 + ahb_podf = __REG(MXC_CCM_CBCDR);
1965 + ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
1966 + MXC_CCM_CBCDR_IPG_PODF_OFFSET;
1967 + ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
1968 + MXC_CCM_CBCDR_AHB_PODF_OFFSET;
1969 + return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
1972 +static u32 __get_ipg_per_clk(void)
1974 + u32 pred1, pred2, podf;
1975 + if (__REG(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
1976 + return __get_ipg_clk();
1977 + /* Fixme: not handle what about lpm*/
1978 + podf = __REG(MXC_CCM_CBCDR);
1979 + pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
1980 + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
1981 + pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
1982 + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
1983 + podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
1984 + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
1986 + return __get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
1990 + * This function returns the low power audio clock.
1992 +static u32 get_lp_apm(void)
1995 + u32 ccsr = __REG(MXC_CCM_CCSR);
1997 + if (((ccsr >> MXC_CCM_CCSR_LP_APM_SEL_OFFSET) & 1) == 0)
1998 + ret_val = CONFIG_MX53_HCLK_FREQ;
2000 + ret_val = ((32768 * 1024));
2005 +static u32 __get_uart_clk(void)
2007 + u32 freq = 0, reg, pred, podf;
2008 + reg = __REG(MXC_CCM_CSCMR1);
2009 + switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
2010 + MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
2012 + freq = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ);
2015 + freq = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ);
2018 + freq = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ);
2021 + freq = get_lp_apm();
2027 + reg = __REG(MXC_CCM_CSCDR1);
2029 + pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
2030 + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
2032 + podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
2033 + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
2034 + freq /= (pred + 1) * (podf + 1);
2040 +static u32 __get_cspi_clk(void)
2042 + u32 ret_val = 0, pdf, pre_pdf, clk_sel, div;
2043 + u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
2044 + u32 cscdr2 = __REG(MXC_CCM_CSCDR2);
2046 + pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
2047 + >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
2048 + pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
2049 + >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
2050 + clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
2051 + >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
2053 + div = (pre_pdf + 1) * (pdf + 1);
2055 + switch (clk_sel) {
2057 + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ) / div;
2060 + ret_val = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ) / div;
2063 + ret_val = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ) / div;
2066 + ret_val = get_lp_apm() / div;
2073 +static u32 __get_axi_a_clk(void)
2075 + u32 cbcdr = __REG(MXC_CCM_CBCDR);
2076 + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
2077 + >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
2079 + return __get_periph_clk() / (pdf + 1);
2082 +static u32 __get_axi_b_clk(void)
2084 + u32 cbcdr = __REG(MXC_CCM_CBCDR);
2085 + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
2086 + >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
2088 + return __get_periph_clk() / (pdf + 1);
2091 +static u32 __get_ahb_clk(void)
2093 + u32 cbcdr = __REG(MXC_CCM_CBCDR);
2094 + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \
2095 + >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
2097 + return __get_periph_clk() / (pdf + 1);
2101 +static u32 __get_emi_slow_clk(void)
2103 + u32 cbcdr = __REG(MXC_CCM_CBCDR);
2104 + u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
2105 + u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
2106 + >> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
2109 + return __get_ahb_clk() / (pdf + 1);
2111 + return __get_periph_clk() / (pdf + 1);
2114 +static u32 __get_ddr_clk(void)
2117 + u32 cbcmr = __REG(MXC_CCM_CBCMR);
2118 + u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
2119 + >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
2121 + switch (ddr_clk_sel) {
2123 + ret_val = __get_axi_a_clk();
2126 + ret_val = __get_axi_b_clk();
2129 + ret_val = __get_emi_slow_clk();
2132 + ret_val = __get_ahb_clk();
2142 +unsigned int mxc_get_clock(enum mxc_clock clk)
2146 + return __get_mcu_main_clk();
2148 + return __get_ahb_clk();
2150 + return __get_ipg_clk();
2151 + case MXC_IPG_PERCLK:
2152 + return __get_ipg_per_clk();
2153 + case MXC_UART_CLK:
2154 + return __get_uart_clk();
2155 + case MXC_CSPI_CLK:
2156 + return __get_cspi_clk();
2157 + case MXC_AXI_A_CLK:
2158 + return __get_axi_a_clk();
2159 + case MXC_AXI_B_CLK:
2160 + return __get_axi_b_clk();
2161 + case MXC_EMI_SLOW_CLK:
2162 + return __get_emi_slow_clk();
2164 + return __get_ddr_clk();
2165 + case MXC_ESDHC_CLK:
2166 + return __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ);
2173 +void mxc_dump_clocks(void)
2176 + freq = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ);
2177 + printf("mx53 pll1: %dMHz\n", freq / 1000000);
2178 + freq = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ);
2179 + printf("mx53 pll2: %dMHz\n", freq / 1000000);
2180 + freq = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ);
2181 + printf("mx53 pll3: %dMHz\n", freq / 1000000);
2182 + printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
2183 + printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
2184 + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
2185 + printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK));
2186 + printf("ahb clock : %dHz\n", mxc_get_clock(MXC_AHB_CLK));
2187 + printf("axi_a clock : %dHz\n", mxc_get_clock(MXC_AXI_A_CLK));
2188 + printf("axi_b clock : %dHz\n", mxc_get_clock(MXC_AXI_B_CLK));
2189 + printf("emi_slow clock: %dHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK));
2190 + printf("ddr clock : %dHz\n", mxc_get_clock(MXC_DDR_CLK));
2193 +#if defined(CONFIG_DISPLAY_CPUINFO)
2194 +int print_cpuinfo(void)
2196 + printf("CPU: Freescale i.MX53 family %d.%dV at %d MHz\n",
2197 + (get_board_rev() & 0xFF) >> 4,
2198 + (get_board_rev() & 0xF),
2199 + __get_mcu_main_clk() / 1000000);
2200 + mxc_dump_clocks();
2205 +#if defined(CONFIG_MXC_FEC)
2206 +extern int mxc_fec_initialize(bd_t *bis);
2207 +extern void mxc_fec_set_mac_from_env(char *mac_addr);
2210 +int cpu_eth_init(bd_t *bis)
2213 +#if defined(CONFIG_MXC_FEC)
2215 + rc = mxc_fec_initialize(bis);
2217 + env = getenv("fec_addr");
2219 + mxc_fec_set_mac_from_env(env);
2224 diff --git a/cpu/arm_cortexa8/mx53/interrupts.c b/cpu/arm_cortexa8/mx53/interrupts.c
2225 new file mode 100644
2226 index 0000000..0b7bd95
2228 +++ b/cpu/arm_cortexa8/mx53/interrupts.c
2231 + * (C) Copyright 2007
2232 + * Sascha Hauer, Pengutronix
2234 + * Copyright (C) 2010 Freescale Semiconductor, Inc.
2236 + * See file CREDITS for list of people who contributed to this
2239 + * This program is free software; you can redistribute it and/or
2240 + * modify it under the terms of the GNU General Public License as
2241 + * published by the Free Software Foundation; either version 2 of
2242 + * the License, or (at your option) any later version.
2244 + * This program is distributed in the hope that it will be useful,
2245 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2246 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2247 + * GNU General Public License for more details.
2249 + * You should have received a copy of the GNU General Public License
2250 + * along with this program; if not, write to the Free Software
2251 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2252 + * MA 02111-1307 USA
2255 +#include <common.h>
2256 +#include <asm/io.h>
2257 +#include <asm/arch/mx53.h>
2259 +/* nothing really to do with interrupts, just starts up a counter. */
2260 +int interrupt_init(void)
2265 +void reset_cpu(ulong addr)
2267 + __REG16(WDOG1_BASE_ADDR) = 4;
2269 diff --git a/cpu/arm_cortexa8/mx53/iomux.c b/cpu/arm_cortexa8/mx53/iomux.c
2270 new file mode 100644
2271 index 0000000..6e52561
2273 +++ b/cpu/arm_cortexa8/mx53/iomux.c
2276 + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
2280 + * The code contained herein is licensed under the GNU General Public
2281 + * License. You may obtain a copy of the GNU General Public License
2282 + * Version 2 or later at the following locations:
2284 + * http://www.opensource.org/licenses/gpl-license.html
2285 + * http://www.gnu.org/copyleft/gpl.html
2289 + * @defgroup GPIO_MX53 Board GPIO and Muxing Setup
2290 + * @ingroup MSL_MX53
2293 + * @file mach-mx53/iomux.c
2295 + * @brief I/O Muxing control functions
2297 + * @ingroup GPIO_MX53
2299 +#include <common.h>
2300 +#include <asm/io.h>
2301 +#include <asm/arch/mx53.h>
2302 +#include <asm/arch/mx53_pins.h>
2303 +#include <asm/arch/iomux.h>
2306 + * IOMUX register (base) addresses
2308 +enum iomux_reg_addr {
2309 + IOMUXGPR0 = IOMUXC_BASE_ADDR,
2310 + IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
2311 + IOMUXGPR2 = IOMUXC_BASE_ADDR + 0x008,
2312 + IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
2313 + IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
2314 + IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
2315 + IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
2318 +static inline u32 _get_mux_reg(iomux_pin_name_t pin)
2320 + u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
2322 + mux_reg += IOMUXSW_MUX_CTL;
2327 +static inline u32 _get_pad_reg(iomux_pin_name_t pin)
2329 + u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
2331 + pad_reg += IOMUXSW_PAD_CTL;
2336 +static inline u32 _get_mux_end(void)
2338 + return IOMUXSW_MUX_END;
2342 + * This function is used to configure a pin through the IOMUX module.
2343 + * FIXED ME: for backward compatible. Will be static function!
2344 + * @param pin a pin number as defined in \b #iomux_pin_name_t
2345 + * @param cfg an output function as defined in \b #iomux_pin_cfg_t
2347 + * @return 0 if successful; Non-zero otherwise
2349 +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
2351 + u32 mux_reg = _get_mux_reg(pin);
2353 + if ((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
2355 + if (cfg == IOMUX_CONFIG_GPIO)
2356 + writel(PIN_TO_ALT_GPIO(pin), mux_reg);
2358 + writel(cfg, mux_reg);
2364 + * Request ownership for an IO pin. This function has to be the first one
2365 + * being called before that pin is used. The caller has to check the
2366 + * return value to make sure it returns 0.
2368 + * @param pin a name defined by \b iomux_pin_name_t
2369 + * @param cfg an input function as defined in \b #iomux_pin_cfg_t
2371 + * @return 0 if successful; Non-zero otherwise
2373 +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
2375 + int ret = iomux_config_mux(pin, cfg);
2381 + * Release ownership for an IO pin
2383 + * @param pin a name defined by \b iomux_pin_name_t
2384 + * @param cfg an input function as defined in \b #iomux_pin_cfg_t
2386 +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
2391 + * This function configures the pad value for a IOMUX pin.
2393 + * @param pin a pin number as defined in \b #iomux_pin_name_t
2394 + * @param config the ORed value of elements defined in \b #iomux_pad_config_t
2396 +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
2398 + u32 pad_reg = _get_pad_reg(pin);
2400 + writel(config, pad_reg);
2403 +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
2405 + u32 pad_reg = _get_pad_reg(pin);
2407 + return readl(pad_reg);
2410 + * This function configures input path.
2412 + * @param input index of input select register as defined in \b
2413 + * #iomux_input_select_t
2414 + * @param config the binary value of elements defined in \b
2415 + * #iomux_input_config_t
2417 +void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
2419 + u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
2421 + writel(config, reg);
2423 diff --git a/cpu/arm_cortexa8/mx53/serial.c b/cpu/arm_cortexa8/mx53/serial.c
2424 new file mode 100644
2425 index 0000000..ce8b5c0
2427 +++ b/cpu/arm_cortexa8/mx53/serial.c
2430 + * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
2432 + * Copyright (C) 2010 Freescale Semiconductor, Inc.
2434 + * This program is free software; you can redistribute it and/or modify
2435 + * it under the terms of the GNU General Public License as published by
2436 + * the Free Software Foundation; either version 2 of the License, or
2437 + * (at your option) any later version.
2439 + * This program is distributed in the hope that it will be useful,
2440 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2441 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2442 + * GNU General Public License for more details.
2444 + * You should have received a copy of the GNU General Public License
2445 + * along with this program; if not, write to the Free Software
2446 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2450 +#include <common.h>
2452 +#if defined CONFIG_MX53_UART
2454 +#include <asm/arch/mx53.h>
2456 +#ifdef CONFIG_MX53_UART1
2457 +#define UART_PHYS UART1_BASE_ADDR
2458 +#elif defined(CONFIG_MX53_UART2)
2459 +#define UART_PHYS UART2_BASE_ADDR
2460 +#elif defined(CONFIG_MX53_UART3)
2461 +#define UART_PHYS UART3_BASE_ADDR
2463 +#error "define CFG_MX53_UARTx to use the mx53 UART driver"
2466 +/* Register definitions */
2467 +#define URXD 0x0 /* Receiver Register */
2468 +#define UTXD 0x40 /* Transmitter Register */
2469 +#define UCR1 0x80 /* Control Register 1 */
2470 +#define UCR2 0x84 /* Control Register 2 */
2471 +#define UCR3 0x88 /* Control Register 3 */
2472 +#define UCR4 0x8c /* Control Register 4 */
2473 +#define UFCR 0x90 /* FIFO Control Register */
2474 +#define USR1 0x94 /* Status Register 1 */
2475 +#define USR2 0x98 /* Status Register 2 */
2476 +#define UESC 0x9c /* Escape Character Register */
2477 +#define UTIM 0xa0 /* Escape Timer Register */
2478 +#define UBIR 0xa4 /* BRM Incremental Register */
2479 +#define UBMR 0xa8 /* BRM Modulator Register */
2480 +#define UBRC 0xac /* Baud Rate Count Register */
2481 +#define UTS 0xb4 /* UART Test Register (mx31) */
2483 +/* UART Control Register Bit Fields.*/
2484 +#define URXD_CHARRDY (1<<15)
2485 +#define URXD_ERR (1<<14)
2486 +#define URXD_OVRRUN (1<<13)
2487 +#define URXD_FRMERR (1<<12)
2488 +#define URXD_BRK (1<<11)
2489 +#define URXD_PRERR (1<<10)
2490 +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
2491 +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
2492 +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
2493 +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
2494 +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
2495 +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
2496 +#define UCR1_IREN (1<<7) /* Infrared interface enable */
2497 +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
2498 +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
2499 +#define UCR1_SNDBRK (1<<4) /* Send break */
2500 +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
2501 +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
2502 +#define UCR1_DOZE (1<<1) /* Doze */
2503 +#define UCR1_UARTEN (1<<0) /* UART enabled */
2504 +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
2505 +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
2506 +#define UCR2_CTSC (1<<13) /* CTS pin control */
2507 +#define UCR2_CTS (1<<12) /* Clear to send */
2508 +#define UCR2_ESCEN (1<<11) /* Escape enable */
2509 +#define UCR2_PREN (1<<8) /* Parity enable */
2510 +#define UCR2_PROE (1<<7) /* Parity odd/even */
2511 +#define UCR2_STPB (1<<6) /* Stop */
2512 +#define UCR2_WS (1<<5) /* Word size */
2513 +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
2514 +#define UCR2_TXEN (1<<2) /* Transmitter enabled */
2515 +#define UCR2_RXEN (1<<1) /* Receiver enabled */
2516 +#define UCR2_SRST (1<<0) /* SW reset */
2517 +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
2518 +#define UCR3_PARERREN (1<<12) /* Parity enable */
2519 +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
2520 +#define UCR3_DSR (1<<10) /* Data set ready */
2521 +#define UCR3_DCD (1<<9) /* Data carrier detect */
2522 +#define UCR3_RI (1<<8) /* Ring indicator */
2523 +#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
2524 +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
2525 +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
2526 +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
2527 +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
2528 +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
2529 +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
2530 +#define UCR3_BPEN (1<<0) /* Preset registers enable */
2531 +#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
2532 +#define UCR4_INVR (1<<9) /* Inverted infrared reception */
2533 +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
2534 +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
2535 +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
2536 +#define UCR4_IRSC (1<<5) /* IR special case */
2537 +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
2538 +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
2539 +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
2540 +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
2541 +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
2542 +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
2543 +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
2544 +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
2545 +#define USR1_RTSS (1<<14) /* RTS pin status */
2546 +#define USR1_TRDY (1<<13)/* Transmitter ready interrupt/dma flag */
2547 +#define USR1_RTSD (1<<12) /* RTS delta */
2548 +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
2549 +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
2550 +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
2551 +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
2552 +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
2553 +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
2554 +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
2555 +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
2556 +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
2557 +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
2558 +#define USR2_IDLE (1<<12) /* Idle condition */
2559 +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
2560 +#define USR2_WAKE (1<<7) /* Wake */
2561 +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
2562 +#define USR2_TXDC (1<<3) /* Transmitter complete */
2563 +#define USR2_BRCD (1<<2) /* Break condition */
2564 +#define USR2_ORE (1<<1) /* Overrun error */
2565 +#define USR2_RDR (1<<0) /* Recv data ready */
2566 +#define UTS_FRCPERR (1<<13) /* Force parity error */
2567 +#define UTS_LOOP (1<<12) /* Loop tx and rx */
2568 +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
2569 +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
2570 +#define UTS_TXFULL (1<<4) /* TxFIFO full */
2571 +#define UTS_RXFULL (1<<3) /* RxFIFO full */
2572 +#define UTS_SOFTRST (1<<0) /* Software reset */
2574 +DECLARE_GLOBAL_DATA_PTR;
2576 +void serial_setbrg(void)
2578 + u32 clk = mxc_get_clock(MXC_UART_CLK);
2580 + if (!gd->baudrate)
2581 + gd->baudrate = CONFIG_BAUDRATE;
2582 + __REG(UART_PHYS + UFCR) = 0x4 << 7; /* divide input clock by 2 */
2583 + __REG(UART_PHYS + UBIR) = 0xf;
2584 + __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
2587 +int serial_getc(void)
2589 + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
2591 + return __REG(UART_PHYS + URXD);
2594 +void serial_putc(const char c)
2596 + __REG(UART_PHYS + UTXD) = c;
2598 + /* wait for transmitter to be ready */
2599 + while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
2602 + /* If \n, also do \r */
2604 + serial_putc('\r');
2608 + * Test whether a character is in the RX buffer
2610 +int serial_tstc(void)
2612 + /* If receive fifo is empty, return false */
2613 + if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
2618 +void serial_puts(const char *s)
2621 + serial_putc(*s++);
2625 + * Initialise the serial port with the given baudrate. The settings
2626 + * are always 8 data bits, no parity, 1 stop bit, no start bits.
2629 +int serial_init(void)
2631 + __REG(UART_PHYS + UCR1) = 0x0;
2632 + __REG(UART_PHYS + UCR2) = 0x0;
2634 + while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST))
2637 + __REG(UART_PHYS + UCR3) = 0x0704;
2638 + __REG(UART_PHYS + UCR4) = 0x8000;
2639 + __REG(UART_PHYS + UESC) = 0x002b;
2640 + __REG(UART_PHYS + UTIM) = 0x0;
2642 + __REG(UART_PHYS + UTS) = 0x0;
2646 + __REG(UART_PHYS + UCR2) =
2647 + UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
2649 + __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
2654 +#endif /* CONFIG_MX53_UART */
2655 diff --git a/cpu/arm_cortexa8/mx53/timer.c b/cpu/arm_cortexa8/mx53/timer.c
2656 new file mode 100644
2657 index 0000000..65ddab9
2659 +++ b/cpu/arm_cortexa8/mx53/timer.c
2662 + * (C) Copyright 2007
2663 + * Sascha Hauer, Pengutronix
2665 + * Copyright (C) 2010 Freescale Semiconductor, Inc.
2667 + * See file CREDITS for list of people who contributed to this
2670 + * This program is free software; you can redistribute it and/or
2671 + * modify it under the terms of the GNU General Public License as
2672 + * published by the Free Software Foundation; either version 2 of
2673 + * the License, or (at your option) any later version.
2675 + * This program is distributed in the hope that it will be useful,
2676 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2677 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2678 + * GNU General Public License for more details.
2680 + * You should have received a copy of the GNU General Public License
2681 + * along with this program; if not, write to the Free Software
2682 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2683 + * MA 02111-1307 USA
2686 +#include <common.h>
2687 +#include <asm/arch/mx53.h>
2689 +/* General purpose timers registers */
2690 +#define GPTCR __REG(GPT1_BASE_ADDR) /* Control register */
2691 +#define GPTPR __REG(GPT1_BASE_ADDR + 0x4) /* Prescaler register */
2692 +#define GPTSR __REG(GPT1_BASE_ADDR + 0x8) /* Status register */
2693 +#define GPTCNT __REG(GPT1_BASE_ADDR + 0x24) /* Counter register */
2695 +/* General purpose timers bitfields */
2696 +#define GPTCR_SWR (1<<15) /* Software reset */
2697 +#define GPTCR_FRR (1<<9) /* Freerun / restart */
2698 +#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */
2699 +#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
2700 +#define GPTCR_TEN (1) /* Timer enable */
2701 +#define GPTPR_VAL (66)
2703 +static inline void setup_gpt(void)
2706 + static int init_done;
2713 + /* setup GP Timer 1 */
2714 + GPTCR = GPTCR_SWR;
2715 + for (i = 0; i < 100; i++)
2716 + GPTCR = 0; /* We have no udelay by now */
2717 + GPTPR = GPTPR_VAL; /* 66Mhz / 66 */
2718 + /* Freerun Mode, PERCLK1 input */
2719 + GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN;
2722 +int timer_init(void)
2729 +void reset_timer_masked(void)
2732 + /* Freerun Mode, PERCLK1 input */
2733 + GPTCR = GPTCR_CLKSOURCE_IPG | GPTCR_TEN;
2736 +inline ulong get_timer_masked(void)
2738 + ulong val = GPTCNT;
2743 +void reset_timer(void)
2745 + reset_timer_masked();
2748 +ulong get_timer(ulong base)
2752 + tmp = get_timer_masked();
2754 + if (tmp <= (base * 1000)) {
2756 + tmp += (0xffffffff - base);
2759 + return (tmp / 1000) - base;
2762 +void set_timer(ulong t)
2766 +/* delay x useconds AND perserve advance timstamp value */
2767 +/* GPTCNT is now supposed to tick 1 by 1 us. */
2768 +void udelay(unsigned long usec)
2774 + tmp = get_timer_masked(); /* get current timestamp */
2776 + /* if setting this forward will roll time stamp */
2777 + if ((usec + tmp + 1) < tmp) {
2778 + /* reset "advancing" timestamp to 0, set lastinc value */
2779 + reset_timer_masked();
2781 + /* else, set advancing stamp wake up time */
2785 + while (get_timer_masked() < tmp) /* loop till event */
2788 diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
2789 index 6732b41..7479c60 100644
2790 --- a/drivers/i2c/mxc_i2c.c
2791 +++ b/drivers/i2c/mxc_i2c.c
2793 #include <asm/arch/mx35.h>
2794 #elif defined(CONFIG_MX51_3DS)
2795 #include <asm/arch/mx51.h>
2796 +#elif defined(CONFIG_MX53)
2797 +#include <asm/arch/mx53.h>
2799 #error "Please include specific headfile "
2801 @@ -233,7 +235,7 @@ static int i2c_addr(uchar chip, uint addr, int alen)
2802 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
2804 int timeout = I2C_MAX_TIMEOUT;
2808 DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",
2809 __func__, chip, addr, alen, len);
2810 diff --git a/drivers/net/mxc_fec.c b/drivers/net/mxc_fec.c
2811 index 314496e..0e6c0b0 100644
2812 --- a/drivers/net/mxc_fec.c
2813 +++ b/drivers/net/mxc_fec.c
2816 DECLARE_GLOBAL_DATA_PTR;
2819 +#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
2821 * * i.MX25 allows RMII mode to be configured via a gasket
2823 @@ -124,6 +124,9 @@ static inline void fec_localhw_setup(volatile fec_t *fecp)
2825 /* re-enable the gasket */
2826 fecp->fec_miigsk_enr = FEC_MIIGSK_ENR_EN;
2828 + while (!(fecp->fec_miigsk_enr & FEC_MIIGSK_ENR_READY))
2832 static inline void fec_localhw_setup(fec_t *fecp)
2833 diff --git a/include/asm-arm/arch-mx53/imx_spi_nor.h b/include/asm-arm/arch-mx53/imx_spi_nor.h
2834 new file mode 100644
2835 index 0000000..9425d59
2837 +++ b/include/asm-arm/arch-mx53/imx_spi_nor.h
2840 + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
2842 + * See file CREDITS for list of people who contributed to this
2845 + * This program is free software; you can redistribute it and/or
2846 + * modify it under the terms of the GNU General Public License as
2847 + * published by the Free Software Foundation; either version 2 of
2848 + * the License, or (at your option) any later version.
2850 + * This program is distributed in the hope that it will be useful,
2851 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2852 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2853 + * GNU General Public License for more details.
2855 + * You should have received a copy of the GNU General Public License
2856 + * along with this program; if not, write to the Free Software
2857 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2858 + * MA 02111-1307 USA
2861 +#ifndef _IMX_SPI_NOR_H_
2862 +#define _IMX_SPI_NOR_H_
2864 +#define READ 0x03 /* tx:1 byte cmd + 3 byte addr;rx:variable bytes */
2865 +#define READ_HS 0x0B /* tx:1 byte cmd + 3 byte addr + 1 byte dummy; */
2866 +#define RDSR 0x05 /* read stat reg 1 byte tx cmd + 1 byte rx status */
2867 +#define RDSR_BUSY (1 << 0) /* 1=write-in-progress (default 0) */
2868 +#define RDSR_WEL (1 << 1) /* 1=write enable (default 0) */
2869 +#define RDSR_BP0 (1 << 2) /* block write prot level (default 1) */
2870 +#define RDSR_BP1 (1 << 3) /* block write prot level (default 1) */
2871 +#define RDSR_BP2 (1 << 4) /* block write prot level (default 1) */
2872 +#define RDSR_BP3 (1 << 5) /* block write prot level (default 1) */
2873 +#define RDSR_AAI (1 << 6) /* 1=AAI prog mode; 0=byte prog (def 0) */
2874 +#define RDSR_BPL (1 << 7) /* 1=BP3,BP2,BP1,BP0 RO; 0=R/W (def 0) */
2875 +#define WREN 0x06 /* write enable. 1 byte tx cmd */
2876 +#define WRDI 0x04 /* write disable. 1 byte tx cmd */
2877 +#define EWSR 0x50 /* Enable write status. 1 byte tx cmd */
2878 +#define WRSR 0x01 /* Write stat reg. 1 byte tx cmd + 1 byte tx val */
2879 +#define ERASE_4K 0x20 /* sector erase. 1 byte cmd + 3 byte addr */
2880 +#define ERASE_32K 0x52 /* 32K block erase. 1 byte cmd + 3 byte addr */
2881 +#define ERASE_64K 0xD8 /* 64K block erase. 1 byte cmd + 3 byte addr */
2882 +#define ERASE_CHIP 0x60 /* whole chip erase */
2883 +#define BYTE_PROG 0x02 /* all tx: 1 cmd + 3 addr + 1 data */
2884 +#define AAI_PROG 0xAD /* all tx: [1 cmd + 3 addr + 2 data] + RDSR */
2885 + /* + [1cmd + 2 data] + .. + [WRDI] + [RDSR] */
2886 +#define JEDEC_ID 0x9F /* read JEDEC ID. tx: 1 byte cmd; rx: 3 byte ID */
2888 +/* Atmel SPI-NOR commands */
2889 +#define WR_2_MEM_DIR 0x82
2890 +#define BUF1_WR 0x84
2891 +#define BUF2_WR 0x87
2892 +#define BUF1_TO_MEM 0x83
2893 +#define BUF2_TO_MEM 0x86
2894 +#define STAT_READ 0xD7
2895 +#define STAT_PG_SZ (1 << 0) /* 1=Page size is 512, 0=Page size is 528 */
2896 +#define STAT_PROT (1 << 1) /* 1=sector protection enabled (default 0) */
2897 +#define STAT_COMP (1 << 6)
2898 +#define STAT_BUSY (1 << 7) /* 1=Device not busy */
2899 +#define CONFIG_REG1 0x3D
2900 +#define CONFIG_REG2 0x2A
2901 +#define CONFIG_REG3 0x80
2902 +#define CONFIG_REG4 0xA6
2904 +#define SZ_64K 0x10000
2905 +#define SZ_32K 0x8000
2906 +#define SZ_4K 0x1000
2908 +#endif /* _IMX_SPI_NOR_H_ */
2909 diff --git a/include/asm-arm/arch-mx53/iomux.h b/include/asm-arm/arch-mx53/iomux.h
2910 new file mode 100644
2911 index 0000000..2184863
2913 +++ b/include/asm-arm/arch-mx53/iomux.h
2916 + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
2918 + * This program is free software; you can redistribute it and/or modify
2919 + * it under the terms of the GNU General Public License as published by
2920 + * the Free Software Foundation; either version 2 of the License, or
2921 + * (at your option) any later version.
2923 + * This program is distributed in the hope that it will be useful,
2924 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2925 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2926 + * GNU General Public License for more details.
2928 + * You should have received a copy of the GNU General Public License along
2929 + * with this program; if not, write to the Free Software Foundation, Inc.,
2930 + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
2933 +#ifndef __MACH_MX53_IOMUX_H__
2934 +#define __MACH_MX53_IOMUX_H__
2936 +#include <common.h>
2937 +#include <asm/io.h>
2938 +#include <asm/arch/mx53.h>
2939 +#include <asm/arch/mx53_pins.h>
2942 + * @file mach-mx53/iomux.h
2944 + * @brief I/O Muxing control definitions and functions
2946 + * @ingroup GPIO_MX53
2949 +typedef unsigned int iomux_pin_name_t;
2952 + * various IOMUX output functions
2954 +typedef enum iomux_config {
2955 + IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
2956 + IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
2957 + IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
2958 + IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
2959 + IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
2960 + IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
2961 + IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
2962 + IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
2963 + IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
2964 + IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
2968 + * various IOMUX pad functions
2970 +typedef enum iomux_pad_config {
2971 + PAD_CTL_SRE_SLOW = 0x0 << 0,
2972 + PAD_CTL_SRE_FAST = 0x1 << 0,
2973 + PAD_CTL_DRV_LOW = 0x0 << 1,
2974 + PAD_CTL_DRV_MEDIUM = 0x1 << 1,
2975 + PAD_CTL_DRV_HIGH = 0x2 << 1,
2976 + PAD_CTL_DRV_MAX = 0x3 << 1,
2977 + PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,
2978 + PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
2979 + PAD_CTL_100K_PD = 0x0 << 4,
2980 + PAD_CTL_47K_PU = 0x1 << 4,
2981 + PAD_CTL_100K_PU = 0x2 << 4,
2982 + PAD_CTL_22K_PU = 0x3 << 4,
2983 + PAD_CTL_PUE_KEEPER = 0x0 << 6,
2984 + PAD_CTL_PUE_PULL = 0x1 << 6,
2985 + PAD_CTL_PKE_NONE = 0x0 << 7,
2986 + PAD_CTL_PKE_ENABLE = 0x1 << 7,
2987 + PAD_CTL_HYS_NONE = 0x0 << 8,
2988 + PAD_CTL_HYS_ENABLE = 0x1 << 8,
2989 + PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,
2990 + PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
2991 + PAD_CTL_DRV_VOT_LOW = 0x0 << 13,
2992 + PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
2993 +} iomux_pad_config_t;
2996 + * various IOMUX input select register index
2998 +typedef enum iomux_input_select {
2999 + MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
3000 + MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
3001 + MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
3002 + MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
3003 + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
3004 + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
3005 + MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
3006 + MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
3007 + MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
3008 + MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
3009 + MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
3010 + MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
3011 + MUX_IN_CAN1_IPP_IND_CANRX_SELECT_INPUT, /*0x760*/
3012 + MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT,
3013 + MUX_IN_CCM_IPP_ASRC_EXT_SELECT_INPUT,
3014 + MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
3015 + MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
3016 + MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
3017 + MUX_IN_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
3018 + MUX_IN_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
3019 + MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, /*0x780*/
3020 + MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
3021 + MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
3022 + MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
3023 + MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
3024 + MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
3025 + MUX_IN_CSPI_IPP_IND_SS_B_4_SELECT_INPUT,
3026 + MUX_IN_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
3027 + MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
3028 + MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
3029 + MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
3030 + MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
3031 + MUX_IN_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT, /*0x7B0*/
3032 + MUX_IN_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT,
3033 + MUX_IN_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
3034 + MUX_IN_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
3035 + MUX_IN_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
3036 + MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
3037 + MUX_IN_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT,
3038 + MUX_IN_ESAI1_IPP_IND_FSR_SELECT_INPUT,
3039 + MUX_IN_ESAI1_IPP_IND_FST_SELECT_INPUT,
3040 + MUX_IN_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
3041 + MUX_IN_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
3042 + MUX_IN_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
3043 + MUX_IN_ESAI1_IPP_IND_SCKT_SELECT_INPUT, /*0x7E0*/
3044 + MUX_IN_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
3045 + MUX_IN_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
3046 + MUX_IN_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
3047 + MUX_IN_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
3048 + MUX_IN_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
3049 + MUX_IN_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
3050 + MUX_IN_ESDHC1_IPP_WP_ON_SELECT_INPUT,
3051 + MUX_IN_FEC_FEC_COL_SELECT_INPUT, /*0x800*/
3052 + MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
3053 + MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
3054 + MUX_IN_FIRI_IPP_IND_RXD_SELECT_INPUT,
3055 + MUX_IN_GPC_PMIC_RDY_SELECT_INPUT,
3056 + MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
3057 + MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
3058 + MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
3059 + MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
3060 + MUX_IN_I2C3_IPP_SCL_IN_SELECT_INPUT,
3061 + MUX_IN_I2C3_IPP_SDA_IN_SELECT_INPUT,
3062 + MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
3063 + MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
3064 + MUX_IN_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
3065 + MUX_IN_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
3066 + MUX_IN_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
3067 + MUX_IN_KPP_IPP_IND_COL_5_SELECT_INPUT, /*0x840*/
3068 + MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
3069 + MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
3070 + MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
3071 + MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
3072 + MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
3073 + MUX_IN_MLB_MLBCLK_IN_SELECT_INPUT,
3074 + MUX_IN_MLB_MLBDAT_IN_SELECT_INPUT,
3075 + MUX_IN_MLB_MLBSIG_IN_SELECT_INPUT,
3076 + MUX_IN_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
3077 + MUX_IN_SDMA_EVENTS_14_SELECT_INPUT,
3078 + MUX_IN_SDMA_EVENTS_15_SELECT_INPUT,
3079 + MUX_IN_SPDIF_SPDIF_IN1_SELECT_INPUT, /*0x870*/
3080 + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
3081 + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
3082 + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
3083 + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
3084 + MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
3085 + MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
3086 + MUX_IN_UART4_IPP_UART_RTS_B_SELECT_INPUT,
3087 + MUX_IN_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
3088 + MUX_IN_UART5_IPP_UART_RTS_B_SELECT_INPUT,
3089 + MUX_IN_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
3090 + MUX_IN_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
3091 + MUX_IN_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
3092 + MUX_IN_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
3093 +} iomux_input_select_t;
3096 + * various IOMUX input functions
3098 +typedef enum iomux_input_config {
3099 + INPUT_CTL_PATH0 = 0x0,
3107 +} iomux_input_config_t;
3109 +struct mxc_iomux_pin_cfg {
3110 + iomux_pin_name_t pin;
3118 + * Request ownership for an IO pin. This function has to be the first one
3119 + * being called before that pin is used. The caller has to check the
3120 + * return value to make sure it returns 0.
3122 + * @param pin a name defined by \b iomux_pin_name_t
3123 + * @param config config as defined in \b #iomux_pin_ocfg_t
3125 + * @return 0 if successful; Non-zero otherwise
3127 +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
3130 + * Release ownership for an IO pin
3132 + * @param pin a name defined by \b iomux_pin_name_t
3133 + * @param config config as defined in \b #iomux_pin_ocfg_t
3135 +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
3138 + * This function configures the pad value for a IOMUX pin.
3140 + * @param pin a pin number as defined in \b #iomux_pin_name_t
3141 + * @param config the ORed value of elements defined in
3142 + * \b #iomux_pad_config_t
3144 +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
3147 + * This function gets the current pad value for a IOMUX pin.
3149 + * @param pin a pin number as defined in \b #iomux_pin_name_t
3150 + * @return current pad value
3152 +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
3155 + * This function configures input path.
3157 + * @param input index of input select register as defined in
3158 + * \b #iomux_input_select_t
3159 + * @param config the binary value of elements defined in \b #iomux_input_config_t
3161 +void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
3163 +#endif /* __MACH_MX53_IOMUX_H__ */
3164 diff --git a/include/asm-arm/arch-mx53/mx53.h b/include/asm-arm/arch-mx53/mx53.h
3165 new file mode 100644
3166 index 0000000..e985357
3168 +++ b/include/asm-arm/arch-mx53/mx53.h
3171 + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3173 + * This program is free software; you can redistribute it and/or modify
3174 + * it under the terms of the GNU General Public License as published by
3175 + * the Free Software Foundation; either version 2 of the License, or
3176 + * (at your option) any later version.
3178 + * This program is distributed in the hope that it will be useful,
3179 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3180 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3181 + * GNU General Public License for more details.
3183 + * You should have received a copy of the GNU General Public License along
3184 + * with this program; if not, write to the Free Software Foundation, Inc.,
3185 + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
3188 +#ifndef __ASM_ARCH_MXC_MX53_H__
3189 +#define __ASM_ARCH_MXC_MX53_H__
3191 +#define __REG(x) (*((volatile u32 *)(x)))
3192 +#define __REG16(x) (*((volatile u16 *)(x)))
3193 +#define __REG8(x) (*((volatile u8 *)(x)))
3198 +#define IRAM_BASE_ADDR 0xF8000000 /* internal ram */
3199 +#define IRAM_PARTITIONS 16
3200 +#define IRAM_SIZE (IRAM_PARTITIONS*SZ_8K) /* 128KB */
3205 +#define NFC_BASE_ADDR_AXI 0xF7FF0000 /* NAND flash AXI */
3206 +#define NFC_AXI_SIZE SZ_64K
3208 +#define TZIC_BASE_ADDR 0x0FFFC000
3210 +#define DEBUG_BASE_ADDR 0x40000000
3211 +#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
3212 +#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
3213 +#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
3214 +#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
3215 +#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
3216 +#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
3217 +#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
3218 +#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
3221 + * SPBA global module enabled #0
3223 +#define SPBA0_BASE_ADDR 0x50000000
3225 +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
3226 +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
3227 +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
3228 +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
3229 +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
3230 +#define ESAI_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
3231 +#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
3232 +#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
3233 +#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
3234 +#define ASRC_BASE_ADDR (SPBA0_BASE_ADDR + 0x0002C000)
3235 +#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
3236 +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
3239 + * defines for SPBA modules
3241 +#define SPBA_SDHC1 0x04
3242 +#define SPBA_SDHC2 0x08
3243 +#define SPBA_UART3 0x0C
3244 +#define SPBA_CSPI1 0x10
3245 +#define SPBA_SSI2 0x14
3246 +#define SPBA_ESAI 0x18
3247 +#define SPBA_SDHC3 0x20
3248 +#define SPBA_SDHC4 0x24
3249 +#define SPBA_SPDIF 0x28
3250 +#define SPBA_ASRC 0x2C
3251 +#define SPBA_ATA 0x30
3252 +#define SPBA_CTRL 0x3C
3257 +#define AIPS1_BASE_ADDR 0x53F00000
3259 +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
3260 +#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
3261 +#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
3262 +#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
3263 +#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
3264 +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
3265 +#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
3266 +#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
3267 +#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
3268 +#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
3269 +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
3270 +#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
3271 +#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
3272 +#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
3273 +#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
3274 +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
3275 +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
3276 +#define CAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C8000)
3277 +#define CAN2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000CC000)
3278 +#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
3279 +#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
3280 +#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
3281 +#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
3282 +#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
3283 +#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
3284 +#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000)
3285 +#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
3286 +#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
3291 +#define AIPS2_BASE_ADDR 0x63F00000
3293 +#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
3294 +#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
3295 +#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
3296 +#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
3297 +#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
3298 +#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
3299 +#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
3300 +#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
3301 +#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
3302 +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
3303 +#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
3304 +#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
3305 +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
3306 +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
3307 +#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
3308 +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
3309 +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
3310 +#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
3311 +#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
3312 +#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
3313 +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
3314 +#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
3315 +#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
3316 +#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
3317 +#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
3318 +#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
3319 +#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
3320 +#define MLB_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
3321 +#define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
3322 +#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
3323 +#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
3324 +#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
3325 +#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
3326 +#define PTP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000FC000)
3329 + * Memory regions and CS
3331 +#define CSD0_BASE_ADDR 0x70000000
3332 +#define CSD1_BASE_ADDR 0xB0000000
3335 + * Interrupt numbers
3337 +#define MXC_INT_BASE 0
3338 +#define MXC_INT_RESV0 0
3339 +#define MXC_INT_MMC_SDHC1 1
3340 +#define MXC_INT_MMC_SDHC2 2
3341 +#define MXC_INT_MMC_SDHC3 3
3342 +#define MXC_INT_MMC_SDHC4 4
3343 +#define MXC_INT_DAP 5
3344 +#define MXC_INT_SDMA 6
3345 +#define MXC_INT_IOMUX 7
3346 +#define MXC_INT_NFC 8
3347 +#define MXC_INT_VPU 9
3348 +#define MXC_INT_IPU_ERR 10
3349 +#define MXC_INT_IPU_SYN 11
3350 +#define MXC_INT_GPU 12
3351 +#define MXC_INT_UART4 13
3352 +#define MXC_INT_USB_H1 14
3353 +#define MXC_INT_EMI 15
3354 +#define MXC_INT_USB_H2 16
3355 +#define MXC_INT_USB_H3 17
3356 +#define MXC_INT_USB_OTG 18
3357 +#define MXC_INT_SAHARA_H0 19
3358 +#define MXC_INT_SAHARA_H1 20
3359 +#define MXC_INT_SCC_SMN 21
3360 +#define MXC_INT_SCC_STZ 22
3361 +#define MXC_INT_SCC_SCM 23
3362 +#define MXC_INT_SRTC_NTZ 24
3363 +#define MXC_INT_SRTC_TZ 25
3364 +#define MXC_INT_RTIC 26
3365 +#define MXC_INT_CSU 27
3366 +#define MXC_INT_SATA 28
3367 +#define MXC_INT_SSI1 29
3368 +#define MXC_INT_SSI2 30
3369 +#define MXC_INT_UART1 31
3370 +#define MXC_INT_UART2 32
3371 +#define MXC_INT_UART3 33
3372 +#define MXC_INT_RTC 34
3373 +#define MXC_INT_PTP 35
3374 +#define MXC_INT_CSPI1 36
3375 +#define MXC_INT_CSPI2 37
3376 +#define MXC_INT_CSPI 38
3377 +#define MXC_INT_GPT 39
3378 +#define MXC_INT_EPIT1 40
3379 +#define MXC_INT_EPIT2 41
3380 +#define MXC_INT_GPIO1_INT7 42
3381 +#define MXC_INT_GPIO1_INT6 43
3382 +#define MXC_INT_GPIO1_INT5 44
3383 +#define MXC_INT_GPIO1_INT4 45
3384 +#define MXC_INT_GPIO1_INT3 46
3385 +#define MXC_INT_GPIO1_INT2 47
3386 +#define MXC_INT_GPIO1_INT1 48
3387 +#define MXC_INT_GPIO1_INT0 49
3388 +#define MXC_INT_GPIO1_LOW 50
3389 +#define MXC_INT_GPIO1_HIGH 51
3390 +#define MXC_INT_GPIO2_LOW 52
3391 +#define MXC_INT_GPIO2_HIGH 53
3392 +#define MXC_INT_GPIO3_LOW 54
3393 +#define MXC_INT_GPIO3_HIGH 55
3394 +#define MXC_INT_GPIO4_LOW 56
3395 +#define MXC_INT_GPIO4_HIGH 57
3396 +#define MXC_INT_WDOG1 58
3397 +#define MXC_INT_WDOG2 59
3398 +#define MXC_INT_KPP 60
3399 +#define MXC_INT_PWM1 61
3400 +#define MXC_INT_I2C1 62
3401 +#define MXC_INT_I2C2 63
3402 +#define MXC_INT_I2C3 64
3403 +#define MXC_INT_MLB 65
3404 +#define MXC_INT_ASRC 66
3405 +#define MXC_INT_SPDIF 67
3406 +#define MXC_INT_RESV1 68
3407 +#define MXC_INT_IIM 69
3408 +#define MXC_INT_ATA 70
3409 +#define MXC_INT_CCM1 71
3410 +#define MXC_INT_CCM2 72
3411 +#define MXC_INT_GPC1 73
3412 +#define MXC_INT_GPC2 74
3413 +#define MXC_INT_SRC 75
3414 +#define MXC_INT_NM 76
3415 +#define MXC_INT_PMU 77
3416 +#define MXC_INT_CTI_IRQ 78
3417 +#define MXC_INT_CTI1_TG0 79
3418 +#define MXC_INT_CTI1_TG1 80
3419 +#define MXC_INT_ESAI 81
3420 +#define MXC_INT_CAN1 82
3421 +#define MXC_INT_CAN2 83
3422 +#define MXC_INT_GPU2_IRQ 84
3423 +#define MXC_INT_GPU2_BUSY 85
3424 +#define MXC_INT_UART5 86
3425 +#define MXC_INT_FEC 87
3426 +#define MXC_INT_OWIRE 88
3427 +#define MXC_INT_CTI1_TG2 89
3428 +#define MXC_INT_SJC 90
3429 +#define MXC_INT_RESV2 91
3430 +#define MXC_INT_TVE 92
3431 +#define MXC_INT_FIRI 93
3432 +#define MXC_INT_PWM2 94
3433 +#define MXC_INT_RESV3 95
3434 +#define MXC_INT_SSI3 96
3435 +#define MXC_INT_RESV4 97
3436 +#define MXC_INT_CTI1_TG3 98
3437 +#define MXC_INT_RESV5 99
3438 +#define MXC_INT_VPU_IDLE 100
3439 +#define MXC_INT_EMI_NFC 101
3440 +#define MXC_INT_GPU_IDLE 102
3441 +#define MXC_INT_GPIO5_LOW 103
3442 +#define MXC_INT_GPIO5_HIGH 104
3443 +#define MXC_INT_GPIO6_LOW 105
3444 +#define MXC_INT_GPIO6_HIGH 106
3445 +#define MXC_INT_GPIO7_LOW 107
3446 +#define MXC_INT_GPIO7_HIGH 108
3448 +/* gpio and gpio based interrupt handling */
3449 +#define GPIO_DR 0x00
3450 +#define GPIO_GDIR 0x04
3451 +#define GPIO_PSR 0x08
3452 +#define GPIO_ICR1 0x0C
3453 +#define GPIO_ICR2 0x10
3454 +#define GPIO_IMR 0x14
3455 +#define GPIO_ISR 0x18
3456 +#define GPIO_INT_LOW_LEV 0x0
3457 +#define GPIO_INT_HIGH_LEV 0x1
3458 +#define GPIO_INT_RISE_EDGE 0x2
3459 +#define GPIO_INT_FALL_EDGE 0x3
3460 +#define GPIO_INT_NONE 0x4
3462 +#define CLKCTL_CCR 0x00
3463 +#define CLKCTL_CCDR 0x04
3464 +#define CLKCTL_CSR 0x08
3465 +#define CLKCTL_CCSR 0x0C
3466 +#define CLKCTL_CACRR 0x10
3467 +#define CLKCTL_CBCDR 0x14
3468 +#define CLKCTL_CBCMR 0x18
3469 +#define CLKCTL_CSCMR1 0x1C
3470 +#define CLKCTL_CSCMR2 0x20
3471 +#define CLKCTL_CSCDR1 0x24
3472 +#define CLKCTL_CS1CDR 0x28
3473 +#define CLKCTL_CS2CDR 0x2C
3474 +#define CLKCTL_CDCDR 0x30
3475 +#define CLKCTL_CHSCDR 0x34
3476 +#define CLKCTL_CSCDR2 0x38
3477 +#define CLKCTL_CSCDR3 0x3C
3478 +#define CLKCTL_CSCDR4 0x40
3479 +#define CLKCTL_CWDR 0x44
3480 +#define CLKCTL_CDHIPR 0x48
3481 +#define CLKCTL_CDCR 0x4C
3482 +#define CLKCTL_CTOR 0x50
3483 +#define CLKCTL_CLPCR 0x54
3484 +#define CLKCTL_CISR 0x58
3485 +#define CLKCTL_CIMR 0x5C
3486 +#define CLKCTL_CCOSR 0x60
3487 +#define CLKCTL_CGPR 0x64
3488 +#define CLKCTL_CCGR0 0x68
3489 +#define CLKCTL_CCGR1 0x6C
3490 +#define CLKCTL_CCGR2 0x70
3491 +#define CLKCTL_CCGR3 0x74
3492 +#define CLKCTL_CCGR4 0x78
3493 +#define CLKCTL_CCGR5 0x7C
3494 +#define CLKCTL_CCGR6 0x80
3495 +#define CLKCTL_CCGR7 0x84
3496 +#define CLKCTL_CMEOR 0x88
3498 +#define CHIP_REV_1_0 0x10
3499 +#define PLATFORM_ICGC 0x14
3501 +/* Assuming 24MHz input clock with doubler ON */
3503 +#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
3504 +#define DP_MFD_850 (48 - 1)
3505 +#define DP_MFN_850 41
3507 +#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
3508 +#define DP_MFD_800 (3 - 1)
3509 +#define DP_MFN_800 1
3511 +#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
3512 +#define DP_MFD_700 (24 - 1)
3513 +#define DP_MFN_700 7
3515 +#define DP_OP_600 ((6 << 4) + ((1 - 1) << 0))
3516 +#define DP_MFD_600 (4 - 1)
3517 +#define DP_MFN_600 1
3519 +#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
3520 +#define DP_MFD_665 (96 - 1)
3521 +#define DP_MFN_665 89
3523 +#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
3524 +#define DP_MFD_532 (24 - 1)
3525 +#define DP_MFN_532 13
3527 +#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
3528 +#define DP_MFD_400 (3 - 1)
3529 +#define DP_MFN_400 1
3531 +#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
3532 +#define DP_MFD_216 (4 - 1)
3533 +#define DP_MFN_216 3
3535 +#define PLL_DP_CTL 0x00
3536 +#define PLL_DP_CONFIG 0x04
3537 +#define PLL_DP_OP 0x08
3538 +#define PLL_DP_MFD 0x0C
3539 +#define PLL_DP_MFN 0x10
3540 +#define PLL_DP_MFNMINUS 0x14
3541 +#define PLL_DP_MFNPLUS 0x18
3542 +#define PLL_DP_HFS_OP 0x1C
3543 +#define PLL_DP_HFS_MFD 0x20
3544 +#define PLL_DP_HFS_MFN 0x24
3545 +#define PLL_DP_TOGC 0x28
3546 +#define PLL_DP_DESTAT 0x2C
3548 +#ifndef __ASSEMBLER__
3571 +enum mxc_peri_clocks {
3584 +extern unsigned int mxc_get_clock(enum mxc_clock clk);
3585 +extern unsigned int get_board_rev(void);
3586 +extern int is_soc_rev(int rev);
3587 +extern enum boot_device get_boot_device(void);
3589 +#endif /* __ASSEMBLER__*/
3591 +#endif /* __ASM_ARCH_MXC_MX53_H__ */
3592 diff --git a/include/asm-arm/arch-mx53/mx53_pins.h b/include/asm-arm/arch-mx53/mx53_pins.h
3593 new file mode 100644
3594 index 0000000..e5afcd7
3596 +++ b/include/asm-arm/arch-mx53/mx53_pins.h
3599 + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3601 + * This program is free software; you can redistribute it and/or modify
3602 + * it under the terms of the GNU General Public License as published by
3603 + * the Free Software Foundation; either version 2 of the License, or
3604 + * (at your option) any later version.
3606 + * This program is distributed in the hope that it will be useful,
3607 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3608 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3609 + * GNU General Public License for more details.
3611 + * You should have received a copy of the GNU General Public License along
3612 + * with this program; if not, write to the Free Software Foundation, Inc.,
3613 + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
3615 +#ifndef __ASM_ARCH_MXC_MX53_PINS_H__
3616 +#define __ASM_ARCH_MXC_MX53_PINS_H__
3619 + * @file arch-mxc/mx53_pins.h
3621 + * @brief MX53 I/O Pin List
3623 + * @ingroup GPIO_MX53
3626 +#ifndef __ASSEMBLY__
3629 + * @name IOMUX/PAD Bit field definitions
3635 + * In order to identify pins more effectively, each mux-controlled pin's
3636 + * enumerated value is constructed in the following way:
3638 + * -------------------------------------------------------------------
3639 + * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
3640 + * -------------------------------------------------------------------
3641 + * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
3642 + * -------------------------------------------------------------------
3644 + * Bit 0 to 9 contains MUX_I used to identify the register
3645 + * offset (0-based. base is IOMUX_module_base) defined in the Section
3646 + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
3647 + * similar field definitions are used for the pad control register.
3648 + * For example, the MX53_PIN_GPIO_19 is defined in the enumeration:
3649 + * ( (0x20 - MUX_I_START) << MUX_I)|( (0x348 - PAD_I_START) << PAD_I)
3650 + * It means the mux control register is at register offset 0x20. The pad control
3651 + * register offset is: 0x348 and also occupy the least significant bits
3652 + * within the register.
3656 + * Starting bit position within each entry of \b iomux_pins to represent the
3657 + * MUX control register offset
3661 + * Starting bit position within each entry of \b iomux_pins to represent the
3662 + * PAD control register offset
3666 + * Starting bit position within each entry of \b iomux_pins to represent which
3667 + * mux mode is for GPIO (0-based)
3671 +#define MUX_IO_P 29
3672 +#define MUX_IO_I 24
3674 +#define NON_GPIO_PORT 0x7
3675 +#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
3676 +#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
3677 +#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
3679 +#define NON_MUX_I PIN_TO_MUX_MASK
3680 +#define NON_PAD_I PIN_TO_PAD_MASK
3681 +#define MUX_I_START 0x0020
3682 +#define PAD_I_START 0x348
3683 +#define INPUT_CTL_START 0x730
3684 +#define MUX_I_END (PAD_I_START - 4)
3686 +#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
3687 + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
3688 + ((mi) << MUX_I) | \
3689 + ((pi - PAD_I_START) << PAD_I) | \
3692 +#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
3693 + _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
3695 +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
3696 + _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
3698 +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
3699 +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
3700 +#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
3701 +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
3703 +/*! @} End IOMUX/PAD Bit field definitions */
3706 + * This enumeration is constructed based on the Section
3707 + * "sw_pad_ctl & sw_mux_ctl details" of the MX53 IC Spec. Each enumerated
3708 + * value is constructed based on the rules described above.
3711 + MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
3712 + MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
3713 + MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
3714 + MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
3715 + MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
3716 + MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
3717 + MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
3718 + MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
3719 + MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
3720 + MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
3721 + MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
3722 + MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
3723 + MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
3724 + MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
3725 + MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
3726 + MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
3727 + MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
3728 + MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
3729 + MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
3730 + MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
3731 + MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
3732 + MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
3733 + MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
3734 + MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
3735 + MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
3736 + MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
3737 + MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
3738 + MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
3739 + MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
3740 + MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
3741 + MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
3742 + MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
3743 + MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
3744 + MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
3745 + MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
3746 + MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
3747 + MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
3748 + MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
3749 + MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
3750 + MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
3751 + MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
3752 + MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
3753 + MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
3754 + MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
3755 + MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
3756 + MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
3757 + MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
3758 + MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
3759 + MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
3760 + MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
3761 + MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
3762 + MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
3763 + MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
3764 + MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
3765 + MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
3766 + MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
3767 + MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
3768 + MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
3769 + MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
3770 + MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
3771 + MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
3772 + MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
3773 + MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
3774 + MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
3775 + MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
3776 + MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
3777 + MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
3778 + MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
3779 + MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
3780 + MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
3781 + MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
3782 + MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
3783 + MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
3784 + MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
3785 + MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
3786 + MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
3787 + MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
3788 + MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
3789 + MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
3790 + MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
3791 + MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
3792 + MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
3793 + MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
3794 + MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
3795 + MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
3796 + MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
3797 + MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
3798 + MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
3799 + MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
3800 + MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
3801 + MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
3802 + MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
3803 + MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
3804 + MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
3805 + MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
3806 + MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
3807 + MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
3808 + MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
3809 + MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
3810 + MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
3811 + MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
3812 + MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
3813 + MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
3814 + MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
3815 + MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
3816 + MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
3817 + MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
3818 + MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
3819 + MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
3820 + MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
3821 + MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
3822 + MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
3823 + MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
3824 + MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
3825 + MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
3826 + MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
3827 + MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
3828 + MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
3829 + MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
3830 + MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
3831 + MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
3832 + MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
3833 + MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
3834 + MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
3835 + MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
3836 + MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
3837 + MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
3838 + MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
3839 + MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
3840 + MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
3841 + MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
3842 + MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
3843 + MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
3844 + MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
3845 + MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
3846 + MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
3847 + MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
3848 + MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
3849 + MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
3850 + MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
3851 + MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
3852 + MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
3853 + MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
3854 + MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
3855 + MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
3856 + MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
3857 + MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
3858 + MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
3859 + MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
3860 + MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
3861 + MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
3862 + MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
3863 + MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
3864 + MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
3865 + MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
3866 + MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
3867 + MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
3868 + MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
3869 + MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
3870 + MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
3871 + MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
3872 + MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
3873 + MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
3874 + MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
3875 + MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
3876 + MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
3877 + MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
3878 + MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
3879 + MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
3880 + MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
3881 + MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
3882 + MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
3883 + MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
3884 + MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
3885 + MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
3886 + MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
3887 + MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
3888 + MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
3889 + MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
3890 + MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
3891 + MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
3892 + MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
3893 + MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
3894 + MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
3895 + MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
3896 + MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
3897 + MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
3898 + MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
3899 + MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
3900 + MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
3901 + MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
3902 + MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
3903 + MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
3904 + MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
3905 + MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
3906 + MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
3907 + MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
3908 + MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
3909 + MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
3910 + MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
3911 + MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
3912 + MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
3913 + MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
3914 + MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
3915 + MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
3916 + MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
3917 + MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
3918 + MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
3919 + MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
3920 + MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
3921 + MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
3922 + MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
3923 + MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
3924 + MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
3925 + MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
3926 + MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
3927 + MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
3928 + MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
3929 + MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
3930 + MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
3931 + MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
3932 + MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
3933 + MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
3934 + MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
3935 + MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
3936 + MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
3937 + MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
3938 + MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
3939 + MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
3940 + MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
3941 + MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
3942 + MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
3943 + MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
3944 + MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
3945 + MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
3946 + MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
3947 + MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
3948 + MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
3949 + MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
3950 + MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
3951 + MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
3952 + MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
3953 + MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
3954 + MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
3955 + MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
3956 + MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
3957 + MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
3958 + MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
3959 + MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
3960 + MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
3961 + MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
3962 + MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
3963 + MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
3964 + MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
3965 + MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
3966 + MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
3967 + MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
3970 +#endif /* __ASSEMBLY__ */
3971 +#endif /* __ASM_ARCH_MXC_MX53_PINS_H__ */
3972 diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
3973 index 5293d67..dc3ec1a 100644
3974 --- a/include/asm-arm/mach-types.h
3975 +++ b/include/asm-arm/mach-types.h
3976 @@ -2241,6 +2241,7 @@ extern unsigned int __machine_arch_type;
3977 #define MACH_TYPE_OMAP3_WL_FF 2258
3978 #define MACH_TYPE_SIMCOM 2259
3979 #define MACH_TYPE_MCWEBIO 2260
3980 +#define MACH_TYPE_MX53_EVK 2716
3982 #ifdef CONFIG_ARCH_EBSA110
3983 # ifdef machine_arch_type
3984 @@ -27406,6 +27407,18 @@ extern unsigned int __machine_arch_type;
3985 # define machine_is_mx51_babbage() (0)
3988 +#ifdef CONFIG_MACH_MX53_EVK
3989 +# ifdef machine_arch_type
3990 +# undef machine_arch_type
3991 +# define machine_arch_type __machine_arch_type
3993 +# define machine_arch_type MACH_TYPE_MX53_EVK
3995 +# define machine_is_mx53_evk() (machine_arch_type == MACH_TYPE_MX53_EVK)
3997 +# define machine_is_mx53_evk() (0)
4000 #ifdef CONFIG_MACH_S3C2440TURKIYE
4001 # ifdef machine_arch_type
4002 # undef machine_arch_type
4003 diff --git a/include/configs/mx53_evk.h b/include/configs/mx53_evk.h
4004 new file mode 100644
4005 index 0000000..010ac76
4007 +++ b/include/configs/mx53_evk.h
4010 + * Copyright (C) 2010 Freescale Semiconductor, Inc.
4012 + * Configuration settings for the MX53-EVK Freescale board.
4014 + * This program is free software; you can redistribute it and/or
4015 + * modify it under the terms of the GNU General Public License as
4016 + * published by the Free Software Foundation; either version 2 of
4017 + * the License, or (at your option) any later version.
4019 + * This program is distributed in the hope that it will be useful,
4020 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4021 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4022 + * GNU General Public License for more details.
4024 + * You should have received a copy of the GNU General Public License
4025 + * along with this program; if not, write to the Free Software
4026 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4027 + * MA 02111-1307 USA
4033 +#include <asm/arch/mx53.h>
4035 + /* High Level Configuration Options */
4036 +#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */
4037 +#define CONFIG_SYS_APCS_GNU
4040 +#define CONFIG_MX53
4041 +#define CONFIG_MX53_EVK
4042 +#define CONFIG_FLASH_HEADER
4043 +#define CONFIG_FLASH_HEADER_OFFSET 0x400
4045 +#define CONFIG_SKIP_RELOCATE_UBOOT
4047 +#define CONFIG_MX53_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
4049 +#define CONFIG_DISPLAY_CPUINFO
4050 +#define CONFIG_DISPLAY_BOARDINFO
4052 +#define BOARD_LATE_INIT
4054 + * Disabled for now due to build problems under Debian and a significant
4055 + * increase in the final file size: 144260 vs. 109536 Bytes.
4058 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
4059 +#define CONFIG_REVISION_TAG 1
4060 +#define CONFIG_SETUP_MEMORY_TAGS 1
4061 +#define CONFIG_INITRD_TAG 1
4064 + * Size of malloc() pool
4066 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
4067 +/* size in bytes reserved for initial data */
4068 +#define CONFIG_SYS_GBL_DATA_SIZE 128
4071 + * Hardware drivers
4073 +#define CONFIG_MX53_UART 1
4074 +#define CONFIG_MX53_UART1 1
4076 +/* allow to overwrite serial and ethaddr */
4077 +#define CONFIG_ENV_OVERWRITE
4078 +#define CONFIG_CONS_INDEX 1
4079 +#define CONFIG_BAUDRATE 115200
4080 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
4082 +/***********************************************************
4083 + * Command definition
4084 + ***********************************************************/
4086 +#include <config_cmd_default.h>
4088 +#define CONFIG_CMD_PING
4089 +#define CONFIG_CMD_DHCP
4090 +#define CONFIG_CMD_MII
4091 +#define CONFIG_CMD_NET
4092 +#define CONFIG_NET_RETRY_COUNT 100
4093 +#define CONFIG_NET_MULTI 1
4094 +#define CONFIG_BOOTP_SUBNETMASK
4095 +#define CONFIG_BOOTP_GATEWAY
4096 +#define CONFIG_BOOTP_DNS
4098 +#define CONFIG_CMD_MMC
4099 +#define CONFIG_CMD_ENV
4101 +#undef CONFIG_CMD_IMLS
4103 +#define CONFIG_BOOTDELAY 3
4105 +#define CONFIG_PRIME "FEC0"
4107 +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
4108 +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
4110 +#define CONFIG_EXTRA_ENV_SETTINGS \
4112 + "ethprime=FEC0\0" \
4113 + "uboot=u-boot.bin\0" \
4114 + "kernel=uImage\0" \
4115 + "nfsroot=/opt/eldk/arm\0" \
4116 + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
4117 + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
4118 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
4119 + "bootcmd_net=run bootargs_base bootargs_nfs; " \
4120 + "tftpboot ${loadaddr} ${kernel}; bootm\0" \
4121 + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \
4122 + "root=/dev/mmcblk0p2 rootwait\0" \
4123 + "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \
4124 + "bootcmd=run bootcmd_net\0" \
4127 +#define CONFIG_ARP_TIMEOUT 200UL
4130 + * Miscellaneous configurable options
4132 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
4133 +#define CONFIG_SYS_PROMPT "EVK U-Boot > "
4134 +#define CONFIG_AUTO_COMPLETE
4135 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
4136 +/* Print Buffer Size */
4137 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
4138 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
4139 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
4141 +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
4142 +#define CONFIG_SYS_MEMTEST_END 0x10000
4144 +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
4146 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
4148 +#define CONFIG_SYS_HZ 1000
4150 +#define CONFIG_CMDLINE_EDITING 1
4152 +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
4153 +#define CONFIG_FEC0_PINMUX -1
4154 +#define CONFIG_FEC0_PHY_ADDR -1
4155 +#define CONFIG_FEC0_MIIBASE -1
4157 +#define CONFIG_MXC_FEC
4159 +#define CONFIG_DISCOVER_PHY
4164 +#define CONFIG_CMD_I2C 1
4165 +#define CONFIG_HARD_I2C 1
4166 +#define CONFIG_I2C_MXC 1
4167 +#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
4168 +#define CONFIG_SYS_I2C_SPEED 100000
4169 +#define CONFIG_SYS_I2C_SLAVE 0xfe
4175 +#define CONFIG_FSL_SF 1
4176 +#define CONFIG_CMD_SPI
4177 +#define CONFIG_CMD_SF
4178 +#define CONFIG_SPI_FLASH_IMX_ATMEL 1
4179 +#define CONFIG_SPI_FLASH_CS 1
4180 +#define CONFIG_IMX_ECSPI
4181 +#define IMX_CSPI_VER_2_3 1
4182 +#define MAX_SPI_BYTES (64 * 4)
4187 +#ifdef CONFIG_CMD_MMC
4188 + #define CONFIG_MMC 1
4189 + #define CONFIG_GENERIC_MMC
4190 + #define CONFIG_IMX_MMC
4191 + #define CONFIG_DOS_PARTITION 1
4192 + #define CONFIG_CMD_FAT 1
4193 + #define CONFIG_CMD_EXT2 1
4195 +/*-----------------------------------------------------------------------
4198 + * The stack sizes are set up in start.S using the settings below
4200 +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
4202 +/*-----------------------------------------------------------------------
4203 + * Physical Memory Map
4205 +#define CONFIG_NR_DRAM_BANKS 1
4206 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR
4207 +#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
4209 +/*-----------------------------------------------------------------------
4210 + * FLASH and environment organization
4212 +#define CONFIG_SYS_NO_FLASH
4214 +/* Monitor at beginning of flash */
4215 +#define CONFIG_FSL_ENV_IN_MMC
4217 +#define CONFIG_ENV_SECT_SIZE (128 * 1024)
4218 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
4220 +#if defined(CONFIG_FSL_ENV_IN_NAND)
4221 + #define CONFIG_ENV_IS_IN_NAND 1
4222 + #define CONFIG_ENV_OFFSET 0x100000
4223 +#elif defined(CONFIG_FSL_ENV_IN_MMC)
4224 + #define CONFIG_ENV_IS_IN_MMC 1
4225 + #define CONFIG_ENV_OFFSET (768 * 1024)
4226 +#elif defined(CONFIG_FSL_ENV_IN_SF)
4227 + #define CONFIG_ENV_IS_IN_SPI_FLASH 1
4228 + #define CONFIG_ENV_SPI_CS 1
4229 + #define CONFIG_ENV_OFFSET (768 * 1024)
4231 + #define CONFIG_ENV_IS_NOWHERE 1
4233 +#endif /* __CONFIG_H */
projects / karo-tx-uboot.git / blob