patches/0114-ENGR00123630-Set-ddr-clk-clock-according-to-the-boar.patch

   1 From af46d9f54b192076c1e3096299d594e2783fc175 Mon Sep 17 00:00:00 2001
   2 From: Jason Liu <r64343@freescale.com>
   3 Date: Wed, 19 May 2010 22:15:05 +0800
   4 Subject: [PATCH] ENGR00123630 Set ddr clk clock according to the board ID
   5
   6 Set DDR clock to 400Mhz on MX53-EVK with DDR2 1GByte RevB
   7 Set DDR clock to 300Mhz on MX53-EVK with DDR2 2GByte RevA1
   8
   9 Remove the clock dump during boot, user can use clk command to
  10 get the clock information. Using help clk to get the command help
  11
  12 Signed-off-by:Jason Liu <r64343@freescale.com>
  13 ---
  14  board/freescale/mx53_evk/mx53_evk.c |   29 ++++++++++++++++++++++++++++-
  15  cpu/arm_cortexa8/mx53/generic.c     |   29 +++++++----------------------
  16  2 files changed, 35 insertions(+), 23 deletions(-)
  17
  18 diff --git a/board/freescale/mx53_evk/mx53_evk.c b/board/freescale/mx53_evk/mx53_evk.c
  19 index 6be0b37..98d5938 100644
  20 --- a/board/freescale/mx53_evk/mx53_evk.c
  21 +++ b/board/freescale/mx53_evk/mx53_evk.c
  22 @@ -44,6 +44,10 @@
  23  #include <asm/arch/mmu.h>
  24  #endif
  25
  26 +#ifdef CONFIG_CMD_CLOCK
  27 +#include <asm/clock.h>
  28 +#endif
  29 +
  30  DECLARE_GLOBAL_DATA_PTR;
  31
  32  static u32 system_rev;
  33 @@ -415,6 +419,25 @@ static int __print_board_info(int id0, int id1)
  34         return ret;
  35  }
  36
  37 +static int _identify_board_fix_up(int id0, int id1)
  38 +{
  39 +       int ret = 0;
  40 +
  41 +#ifdef CONFIG_CMD_CLOCK
  42 +       /* For EVK RevB, set DDR to 400MHz */
  43 +       if (id0 == 21 && id1 == 15) {
  44 +               ret = clk_config(CONFIG_REF_CLK_FREQ, 400, PERIPH_CLK);
  45 +               if (ret < 0)
  46 +                       return ret;
  47 +
  48 +               ret = clk_config(CONFIG_REF_CLK_FREQ, 400, DDR_CLK);
  49 +               if (ret < 0)
  50 +                       return ret;
  51 +       }
  52 +#endif
  53 +       return ret;
  54 +}
  55 +
  56  int identify_board_id(void)
  57  {
  58         int ret = 0;
  59 @@ -440,6 +463,10 @@ int identify_board_id(void)
  60                 return ret;
  61
  62         ret = __print_board_info(bd_id0, bd_id1);
  63 +       if (ret < 0)
  64 +               return ret;
  65 +
  66 +       ret = _identify_board_fix_up(bd_id0, bd_id1);
  67
  68         return ret;
  69
  70 @@ -682,7 +709,7 @@ int board_late_init(void)
  71
  72  int checkboard(void)
  73  {
  74 -       printf("Board:   ");
  75 +       printf("Board: ");
  76
  77  #ifdef CONFIG_I2C_MXC
  78         identify_board_id();
  79 diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c
  80 index 26a7894..791c0c3 100644
  81 --- a/cpu/arm_cortexa8/mx53/generic.c
  82 +++ b/cpu/arm_cortexa8/mx53/generic.c
  83 @@ -641,8 +641,8 @@ int clk_info(u32 clk_type)
  84                         mxc_get_clock(MXC_DDR_CLK));
  85                 break;
  86         case ALL_CLK:
  87 -               printf("cpu clock: %dHz\n",
  88 -                       mxc_get_clock(MXC_ARM_CLK));
  89 +               printf("cpu clock: %dMHz\n",
  90 +                       mxc_get_clock(MXC_ARM_CLK) / SZ_DEC_1M);
  91                 mxc_dump_clocks();
  92                 break;
  93         default:
  94 @@ -702,6 +702,8 @@ u32 calc_per_cbcdr_val(u32 per_clk, u32 cbcmr)
  95
  96  #define CHANGE_PLL_SETTINGS(base, pd, mfi, mfn, mfd) \
  97         {       \
  98 +               writel(0x1232, base + PLL_DP_CTL); \
  99 +               writel(0x2, base + PLL_DP_CONFIG);    \
 100                 writel(((pd - 1) << 0) | (mfi << 4),    \
 101                         base + PLL_DP_OP);      \
 102                 writel(mfn, base + PLL_DP_MFN); \
 103 @@ -710,6 +712,9 @@ u32 calc_per_cbcdr_val(u32 per_clk, u32 cbcmr)
 104                         base + PLL_DP_HFS_OP);  \
 105                 writel(mfn, base + PLL_DP_HFS_MFN);     \
 106                 writel(mfd - 1, base + PLL_DP_HFS_MFD); \
 107 +               writel(0x1232, base + PLL_DP_CTL); \
 108 +               while (!readl(base + PLL_DP_CTL) & 0x1)  \
 109 +                       ; \
 110         }
 111
 112  int config_pll_clk(enum pll_clocks pll, struct pll_param *pll_param)
 113 @@ -815,15 +820,6 @@ int config_periph_clk(u32 ref, u32 freq)
 114                 u32 old_cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
 115                 u32 cbcdr = 0;
 116
 117 -               /* Set PLL3 to 400MHz */
 118 -               ret = calc_pll_params(ref, 400000000, &pll_param);
 119 -               if (ret != 0) {
 120 -                       printf("Can't find pll parameters: %d\n",
 121 -                               ret);
 122 -                       return ret;
 123 -               }
 124 -               config_pll_clk(PLL3_CLK, &pll_param);
 125 -
 126                 /* Switch peripheral to PLL3 */
 127                 writel(0x00015154, CCM_BASE_ADDR + CLKCTL_CBCMR);
 128                 writel(0x02888945, CCM_BASE_ADDR + CLKCTL_CBCDR);
 129 @@ -850,16 +846,6 @@ int config_periph_clk(u32 ref, u32 freq)
 130                 /* Make sure change is effective */
 131                 while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
 132                         ;
 133 -
 134 -               /* Switch PLL3's freq back */
 135 -               ret = calc_pll_params(ref, pll3_freq, &pll_param);
 136 -               if (ret != 0) {
 137 -                       printf("Can't find pll parameters: %d\n",
 138 -                               ret);
 139 -                       return ret;
 140 -               }
 141 -               config_pll_clk(PLL3_CLK, &pll_param);
 142 -
 143                 puts("\n");
 144         }
 145
 146 @@ -974,7 +960,6 @@ int print_cpuinfo(void)
 147                (get_board_rev() & 0xFF) >> 4,
 148                (get_board_rev() & 0xF),
 149                 __get_mcu_main_clk() / 1000000);
 150 -       mxc_dump_clocks();
 151         return 0;
 152  }
 153  #endif
 154 --
 155 1.5.4.4
 156