Table of interleaving modes supported in cpu/8xxx/ddr/
======================================================
  +-------------+---------------------------------------------------------+
  |             |                   Rank Interleaving                     |
  |             +--------+-----------+-----------+------------+-----------+
  |Memory       |        |           |           |    2x2     |    4x1    |
  |Controller   |  None  | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
  |Interleaving |        | {CS0+CS1} | {CS2+CS3} | {CS2+CS3}  |  CS2+CS3} |
  +-------------+--------+-----------+-----------+------------+-----------+
  |None         |  Yes   | Yes       | Yes       | Yes        | Yes       |
  +-------------+--------+-----------+-----------+------------+-----------+
  |Cacheline    |  Yes   | Yes       | No        | No, Only(*)| Yes       |
  |             |CS0 Only|           |           | {CS0+CS1}  |           |
  +-------------+--------+-----------+-----------+------------+-----------+
  |Page         |  Yes   | Yes       | No        | No, Only(*)| Yes       |
  |             |CS0 Only|           |           | {CS0+CS1}  |           |
  +-------------+--------+-----------+-----------+------------+-----------+
  |Bank         |  Yes   | Yes       | No        | No, Only(*)| Yes       |
  |             |CS0 Only|           |           | {CS0+CS1}  |           |
  +-------------+--------+-----------+-----------+------------+-----------+
  |Superbank    |  No    | Yes       | No        | No, Only(*)| Yes       |
  |             |        |           |           | {CS0+CS1}  |           |
  +-------------+--------+-----------+-----------+------------+-----------+
 (*) Although the hardware can be configured with memory controller
 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
 from each controller. {CS2+CS3} on each controller are only rank
 interleaved on that controller.

The ways to configure the ddr interleaving mode
==============================================
1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
   under "CONFIG_EXTRA_ENV_SETTINGS", like:
	#define CONFIG_EXTRA_ENV_SETTINGS				\
	 "hwconfig=fsl_ddr:ctlr_intlv=bank"			\
	 ......

2. Run u-boot "setenv" command to configure the memory interleaving mode.
   Either numerical or string value is accepted.

  # disable memory controller interleaving
  setenv hwconfig "fsl_ddr:ctlr_intlv=null"

  # cacheline interleaving
  setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"

  # page interleaving
  setenv hwconfig "fsl_ddr:ctlr_intlv=page"

  # bank interleaving
  setenv hwconfig "fsl_ddr:ctlr_intlv=bank"

  # superbank
  setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"

  # disable bank (chip-select) interleaving
  setenv hwconfig "fsl_ddr:bank_intlv=null"

  # bank(chip-select) interleaving cs0+cs1
  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"

  # bank(chip-select) interleaving cs2+cs3
  setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"

  # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3)  (2x2)
  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"

  # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"

  The above memory controller interleaving and bank interleaving can be mixed. The syntax is
  setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1"