U-Boot for UniPhier SoC family ============================== Tested toolchains ----------------- (a) Ubuntu packages (CROSS_COMPILE=arm-linux-gnueabi-) If you are building U-Boot on Ubuntu, its standard package is recommended. You can install it as follows: $ sudo apt-get install gcc-arm-linux-gnueabi- (b) Linaro compilers (CROSS_COMPILE=arm-linux-gnueabihf-) You can download pre-built toolchains from: http://www.linaro.org/downloads/ (c) kernel.org compilers (CROSS_COMPILE=arm-unknown-linux-gnueabi-) You can download pre-built toolchains from: ftp://www.kernel.org/pub/tools/crosstool/files/bin/ Compile the source ------------------ PH1-sLD3: $ make ph1_sld3_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- PH1-LD4: $ make ph1_ld4_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- PH1-Pro4: $ make ph1_pro4_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- PH1-sLD8: $ make ph1_sld8_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-" to use your favorite compiler. Burn U-Boot images to NAND -------------------------- Write two files to the NAND device as follows: - spl/u-boot-spl.bin at the offset address 0x00000000 - u-boot-dtb.img at the offset address 0x00010000 If a TFTP server is available, the images can be easily updated. Just copy the u-boot-spl.bin and u-boot-dtb.img to the TFTP public directory, and then run the following command at the U-Boot command line: => run nandupdate UniPhier specific commands -------------------------- - pinmon (enabled by CONFIG_CMD_PINMON) shows the boot mode pins that has been latched at the power-on reset - ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP) shows the DDR PHY parameters set by the PHY training Supported devices ----------------- - UART (on-chip) - NAND - USB 2.0 (EHCI) - USB 3.0 (xHCI) - LAN (on-board SMSC9118) - I2C - EEPROM (connected to the on-board I2C bus) - Support card (SRAM, NOR flash, some peripherals) Micro Support Card ------------------ The recommended bit switch settings are as follows: SW2 OFF(1)/ON(0) Description ------------------------------------------ bit 1 <---- BKSZ[0] bit 2 ----> BKSZ[1] bit 3 <---- SoC Bus Width 16/32 bit 4 <---- SERIAL_SEL[0] bit 5 ----> SERIAL_SEL[1] bit 6 ----> BOOTSWAP_EN bit 7 <---- CS1/CS5 bit 8 <---- SOC_SERIAL_DISABLE SW8 OFF(1)/ON(0) Description ------------------------------------------ bit 1 ----> CS1_SPLIT bit 2 <---- CASE9_ON bit 3 <---- CASE10_ON bit 4 Don't Care Reserve bit 5 Don't Care Reserve bit 6 Don't Care Reserve bit 7 ----> BURST_EN bit 8 ----> FLASHBUS32_16 The BKSZ[1:0] specifies the address range of memory slot and peripherals as follows: BKSZ Description RAM slot Peripherals -------------------------------------------------------------------- 0b00 15MB RAM / 1MB Peri 00000000-0effffff 0f000000-0fffffff 0b01 31MB RAM / 1MB Peri 00000000-1effffff 1f000000-1fffffff 0b10 64MB RAM / 1MB Peri 00000000-3effffff 3f000000-3fffffff 0b11 127MB RAM / 1MB Peri 00000000-7effffff 7f000000-7fffffff Set BSKZ[1:0] to 0b01 for U-Boot. This mode is the most handy because EA[24] is always supported by the save pin mode of the system bus. On the other hand, EA[25] is not supported for some newer SoCs. Even if it is, EA[25] is not connected on most of the boards. -- Masahiro Yamada Jul. 2015