arm: omap3: cm-t35: convert to generic board

[karo-tx-uboot.git] / README

diff --git a/README b/README
index 66770b648539701fe0fdd8b36b1076359557ddd3..00cd05520c1f02c77b6655641034aadf132c1f4c 100644 (file)
--- a/README
+++ b/README
@@ -186,7 +186,6 @@ Directory Hierarchy:
       /mpc5xx          Files specific to Freescale MPC5xx CPUs
       /mpc5xxx         Files specific to Freescale MPC5xxx CPUs
       /mpc8xx          Files specific to Freescale MPC8xx CPUs
-      /mpc824x         Files specific to Freescale MPC824x CPUs
       /mpc8260         Files specific to Freescale MPC8260 CPUs
       /mpc85xx         Files specific to Freescale MPC85xx CPUs
       /ppc4xx          Files specific to AMCC PowerPC 4xx CPUs
@@ -326,10 +325,6 @@ The following options need to be configured:
                                          multiple fs option at one time
                                          for marvell soc family
 
-- MPC824X Family Member (if CONFIG_MPC824X is defined)
-               Define exactly one of
-               CONFIG_MPC8240, CONFIG_MPC8245
-
 - 8xx CPU Options: (if using an MPC8xx CPU)
                CONFIG_8xx_GCLK_FREQ    - deprecated: CPU clock if
                                          get_gclk_freq() cannot work
@@ -409,6 +404,10 @@ The following options need to be configured:
                Enables a workaround for IFC erratum A003399. It is only
                requred during NOR boot.
 
+               CONFIG_A008044_WORKAROUND
+               Enables a workaround for T1040/T1042 erratum A008044. It is only
+               requred during NAND boot and valid for Rev 1.0 SoC revision
+
                CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 
                This is the value to write into CCSR offset 0x18600
@@ -1769,6 +1768,15 @@ The following options need to be configured:
                regarding the non-volatile storage device. Define this to
                the eMMC device that fastboot should use to store the image.
 
+               CONFIG_FASTBOOT_GPT_NAME
+               The fastboot "flash" command supports writing the downloaded
+               image to the Protective MBR and the Primary GUID Partition
+               Table. (Additionally, this downloaded image is post-processed
+               to generate and write the Backup GUID Partition Table.)
+               This occurs when the specified "partition name" on the
+               "fastboot flash" command line matches this value.
+               Default is GPT_ENTRY_NAME (currently "gpt") if undefined.
+
 - Journaling Flash filesystem support:
                CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
                CONFIG_JFFS2_NAND_DEV
@@ -3657,10 +3665,13 @@ FIT uImage format:
 
                CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
                CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
-               CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION
-               Address, size and partition on the MMC to load U-Boot from
+               Address and partition on the MMC to load U-Boot from
                when the MMC is being used in raw mode.
 
+               CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+               Partition on the MMC to load U-Boot from when the MMC is being
+               used in raw mode
+
                CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
                Sector to load kernel uImage from when MMC is being
                used in raw mode (for Falcon mode)
@@ -3671,6 +3682,10 @@ FIT uImage format:
                parameters from when MMC is being used in raw mode
                (for falcon mode)
 
+               CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
+               Partition on the MMC to load U-Boot from when the MMC is being
+               used in fs mode
+
                CONFIG_SPL_FAT_SUPPORT
                Support for fs/fat/libfat.o in SPL binary
 
@@ -3996,6 +4011,25 @@ Configuration Settings:
                boards which do not use the full malloc in SPL (which is
                enabled with CONFIG_SYS_SPL_MALLOC_START).
 
+- CONFIG_SYS_NONCACHED_MEMORY:
+               Size of non-cached memory area. This area of memory will be
+               typically located right below the malloc() area and mapped
+               uncached in the MMU. This is useful for drivers that would
+               otherwise require a lot of explicit cache maintenance. For
+               some drivers it's also impossible to properly maintain the
+               cache. For example if the regions that need to be flushed
+               are not a multiple of the cache-line size, *and* padding
+               cannot be allocated between the regions to align them (i.e.
+               if the HW requires a contiguous array of regions, and the
+               size of each region is not cache-aligned), then a flush of
+               one region may result in overwriting data that hardware has
+               written to another region in the same cache-line. This can
+               happen for example in network drivers where descriptors for
+               buffers are typically smaller than the CPU cache-line (e.g.
+               16 bytes vs. 32 or 64 bytes).
+
+               Non-cached memory is only supported on 32-bit ARM at present.
+
 - CONFIG_SYS_BOOTM_LEN:
                Normally compressed uImages are limited to an
                uncompressed size of 8 MBytes. If this is not enough,