Merge branch 'next' of git://git.denx.de/u-boot-sh

[karo-tx-uboot.git] / README

diff --git a/README b/README
index cb96322fb71d0e4301182759fa53c4afdc6b3167..12758dc6e793f3fb27b0520ea7127788921308a2 100644 (file)
--- a/README
+++ b/README
@@ -132,6 +132,10 @@ Directory Hierarchy:
 ====================
 
 /arch                  Architecture specific files
+  /arc                 Files generic to ARC architecture
+    /cpu               CPU specific files
+      /arc700          Files specific to ARC 700 CPUs
+    /lib               Architecture specific library files
   /arm                 Files generic to ARM architecture
     /cpu               CPU specific files
       /arm720t         Files specific to ARM 720 CPUs
@@ -164,7 +168,7 @@ Directory Hierarchy:
   /mips                        Files generic to MIPS architecture
     /cpu               CPU specific files
       /mips32          Files specific to MIPS32 CPUs
-      /xburst          Files specific to Ingenic XBurst CPUs
+      /mips64          Files specific to MIPS64 CPUs
     /lib               Architecture specific library files
   /nds32               Files generic to NDS32 architecture
     /cpu               CPU specific files
@@ -431,6 +435,10 @@ The following options need to be configured:
                This CONFIG is defined when the CPC is configured as SRAM at the
                time of U-boot entry and is required to be re-initialized.
 
+               CONFIG_DEEP_SLEEP
+               Inidcates this SoC supports deep sleep feature. If deep sleep is
+               supported, core will start to execute uboot when wakes up.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -458,6 +466,9 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DDRC_GEN3
                Freescale DDR3 controller.
 
+               CONFIG_SYS_FSL_DDRC_GEN4
+               Freescale DDR4 controller.
+
                CONFIG_SYS_FSL_DDRC_ARM_GEN3
                Freescale DDR3 controller for ARM-based SoCs.
 
@@ -473,7 +484,15 @@ The following options need to be configured:
 
                CONFIG_SYS_FSL_DDR3
                Board config to use DDR3. It can be enabled for SoCs with
-               Freescale DDR3 controllers.
+               Freescale DDR3 or DDR3L controllers.
+
+               CONFIG_SYS_FSL_DDR3L
+               Board config to use DDR3L. It can be enabled for SoCs with
+               DDR3L controllers.
+
+               CONFIG_SYS_FSL_DDR4
+               Board config to use DDR4. It can be enabled for SoCs with
+               DDR4 controllers.
 
                CONFIG_SYS_FSL_IFC_BE
                Defines the IFC controller register space as Big Endian
@@ -490,6 +509,10 @@ The following options need to be configured:
                PBI commands can be used to configure SoC before it starts the execution.
                Please refer doc/README.pblimage for more details
 
+               CONFIG_SPL_FSL_PBL
+               It adds a target to create boot binary having SPL binary in PBI format
+               concatenated with u-boot binary.
+
                CONFIG_SYS_FSL_DDR_BE
                Defines the DDR controller register space as Big Endian
 
@@ -3317,6 +3340,9 @@ FIT uImage format:
                continuing (the hardware starts execution after just
                loading the first page rather than the full 4K).
 
+               CONFIG_SPL_SKIP_RELOCATE
+               Avoid SPL relocation
+
                CONFIG_SPL_NAND_BASE
                Include nand_base.c in the SPL.  Requires
                CONFIG_SPL_NAND_DRIVERS.