DECLARE_GLOBAL_DATA_PTR;
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
-inline void lowlevel_init(void) {}
+void lowlevel_init(void) {}
#define BOOT_CAUSE_MASK (RTC_PERSISTENT0_EXTERNAL_RESET | \
RTC_PERSISTENT0_ALARM_WAKE | \
*/
void mx28_fixup_vt(uint32_t start_addr)
{
- /* ldr pc, [pc, #0x18] */
- const uint32_t ldr_pc = 0xe59ff018;
/* Jumptable location is 0x0 */
- uint32_t *vt = (uint32_t *)0x0;
- int i;
+ uint32_t *vt = (uint32_t *)0x20;
+ uint32_t cr = get_cr();
- for (i = 0; i < 8; i++) {
- vt[i] = ldr_pc;
- vt[i + 8] = start_addr + (4 * i);
- }
+ /* cppcheck-suppress nullPointer */
+ memcpy(vt, (void *)start_addr + 0x20, 32);
+ set_cr(cr & ~CR_V);
}
#ifdef CONFIG_ARCH_MISC_INIT
}
#endif
+#define pr_clk(n, c) { \
+ unsigned long clk = c; \
+ printf("%-5s %3lu.%03lu MHz\n", #n ":", clk / 1000000, \
+ clk / 1000 % 1000); \
+}
+
int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
- printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
- printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
- printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
- printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
+ pr_clk(CPU, mxc_get_clock(MXC_ARM_CLK));
+ pr_clk(APBH, mxc_get_clock(MXC_AHB_CLK));
+ pr_clk(APBX, mxc_get_clock(MXC_XBUS_CLK));
+ pr_clk(IO0, mxc_get_clock(MXC_IO0_CLK) * 1000);
+ pr_clk(IO1, mxc_get_clock(MXC_IO1_CLK) * 1000);
+ pr_clk(EMI, mxc_get_clock(MXC_EMI_CLK) * 1000000);
+ pr_clk(GPMI, mxc_get_clock(MXC_GPMI_CLK));
return 0;
}
/*
* Initializes on-chip ethernet controllers.
*/
-#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
+#if defined(CONFIG_SOC_MX28) && defined(CONFIG_CMD_NET)
int cpu_eth_init(bd_t *bis)
{
struct mxs_clkctrl_regs *clkctrl_regs =
writel(CLKCTRL_PLL2CTRL0_CLKGATE,
&clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
+ udelay(6000);
return 0;
}
#endif