karo: merge with Ka-Ro specific tree for secure boot support

[karo-tx-uboot.git] / arch / arm / cpu / arm926ejs / mxs / timer.c

diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c
index 12789327ccb65dbcb18b5b3c5eb66be53dd17a8e..021e21f93928b07fa5b9597fd21fd823f1cfdb59 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/timer.c
+++ b/arch/arm/cpu/arm926ejs/mxs/timer.c
@@ -7,7 +7,7 @@
  * Based on code from LTIB:
  * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
  *
- * SPDX-License-Identifier:    GPL-2.0+ 
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -74,31 +74,36 @@ int timer_init(void)
                TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL,
                &timrot_regs->hw_timrot_timctrl0);
 
+#ifndef DEBUG_TIMER_WRAP
        /* Set fixed_count to maximum value */
 #if defined(CONFIG_MX23)
        writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
 #elif defined(CONFIG_MX28)
        writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
 #endif
-
-#ifndef DEBUG_TIMER_WRAP
-       /* Set fixed_count to maximum value */
-       writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
-#else
+#else /* DEBUG_TIMER_WRAP */
        /* Set fixed_count so that the counter will wrap after 20 seconds */
+#if defined(CONFIG_MX23)
+       writel(20 * MXS_INCREMENTER_HZ - 1, &timrot_regs->hw_timrot_timcount0);
+#elif defined(CONFIG_MX28)
        writel(20 * MXS_INCREMENTER_HZ,
                &timrot_regs->hw_timrot_fixed_count0);
+#endif
        gd->arch.lastinc = TIMER_LOAD_VAL - 20 * MXS_INCREMENTER_HZ;
 
        /* Make the usec counter roll over 30 seconds after startup */
        writel(-30000000, MXS_HW_DIGCTL_MICROSECONDS);
-#endif
+#endif /* DEBUG_TIMER_WRAP */
        writel(TIMROT_TIMCTRLn_UPDATE,
                &timrot_regs->hw_timrot_timctrl0_clr);
 #ifdef DEBUG_TIMER_WRAP
-       /* Set fixed_count to maximal value for subsequent loads */
+       /* Set fixed_count to maximum value for subsequent loads */
+#if defined(CONFIG_MX23)
+       writel(20 * MXS_INCREMENTER_HZ - 1, &timrot_regs->hw_timrot_timcount0);
+#elif defined(CONFIG_MX28)
        writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
 #endif
+#endif /* DEBUG_TIMER_WRAP */
        gd->arch.timer_rate_hz = MXS_INCREMENTER_HZ;
        gd->arch.tbl = TIMER_START;
        gd->arch.tbu = 0;
@@ -120,12 +125,14 @@ unsigned long long get_ticks(void)
        /* Upper bits are the valid ones. */
        now = readl(&timrot_regs->hw_timrot_timcount0) >>
                TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
-#else
+#elif defined(CONFIG_MX28)
        /* The timer is counting down, so subtract the register value from
         * the counter period length (implicitly 2^32) to get an incrementing
         * timestamp
         */
        now = -readl(&timrot_regs->hw_timrot_running_count0);
+#else
+#error "Don't know how to read timrot_regs"
 #endif
        ulong inc = now - gd->arch.lastinc;