Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / am33xx / board.c

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index e4c123cd21d614f3b2bee6a3aabf6a9e5288be56..b935a29a3ca18aeec87287c4329925037562f348 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -25,6 +25,7 @@
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
@@ -33,6 +34,11 @@
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
+#include <asm/errno.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -50,11 +56,11 @@ int cpu_mmc_init(bd_t *bis)
 {
        int ret;
 
-       ret = omap_mmc_init(0, 0, 0);
+       ret = omap_mmc_init(0, 0, 0, -1, -1);
        if (ret)
                return ret;
 
-       return omap_mmc_init(1, 0, 0);
+       return omap_mmc_init(1, 0, 0, -1, -1);
 }
 #endif
 
@@ -63,3 +69,123 @@ void setup_clocks_for_console(void)
        /* Not yet implemented */
        return;
 }
+
+/* AM33XX has two MUSB controllers which can be host or gadget */
+#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
+       (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* USB 2.0 PHY Control */
+#define CM_PHY_PWRDN                   (1 << 0)
+#define CM_PHY_OTG_PWRDN               (1 << 1)
+#define OTGVDET_EN                     (1 << 19)
+#define OTGSESSENDEN                   (1 << 20)
+
+static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
+{
+       if (on) {
+               clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
+                               OTGVDET_EN | OTGSESSENDEN);
+       } else {
+               clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
+       }
+}
+
+static struct musb_hdrc_config musb_config = {
+       .multipoint     = 1,
+       .dyn_fifo       = 1,
+       .num_eps        = 16,
+       .ram_bits       = 12,
+};
+
+#ifdef CONFIG_AM335X_USB0
+static void am33xx_otg0_set_phy_power(u8 on)
+{
+       am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
+}
+
+struct omap_musb_board_data otg0_board_data = {
+       .set_phy_power = am33xx_otg0_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg0_plat = {
+       .mode           = CONFIG_AM335X_USB0_MODE,
+       .config         = &musb_config,
+       .power          = 50,
+       .platform_ops   = &musb_dsps_ops,
+       .board_data     = &otg0_board_data,
+};
+#endif
+
+#ifdef CONFIG_AM335X_USB1
+static void am33xx_otg1_set_phy_power(u8 on)
+{
+       am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
+}
+
+struct omap_musb_board_data otg1_board_data = {
+       .set_phy_power = am33xx_otg1_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg1_plat = {
+       .mode           = CONFIG_AM335X_USB1_MODE,
+       .config         = &musb_config,
+       .power          = 50,
+       .platform_ops   = &musb_dsps_ops,
+       .board_data     = &otg1_board_data,
+};
+#endif
+#endif
+
+int arch_misc_init(void)
+{
+#ifdef CONFIG_AM335X_USB0
+       musb_register(&otg0_plat, &otg0_board_data,
+               (void *)USB0_OTG_BASE);
+#endif
+#ifdef CONFIG_AM335X_USB1
+       musb_register(&otg1_plat, &otg1_board_data,
+               (void *)USB1_OTG_BASE);
+#endif
+       return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void rtc32k_enable(void)
+{
+       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+       /*
+        * Unlock the RTC's registers.  For more details please see the
+        * RTC_SS section of the TRM.  In order to unlock we need to
+        * write these specific values (keys) in this order.
+        */
+       writel(0x83e70b13, &rtc->kick0r);
+       writel(0x95a4f1e0, &rtc->kick1r);
+
+       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
+       writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+#define UART_RESET             (0x1 << 1)
+#define UART_CLK_RUNNING_MASK  0x1
+#define UART_SMART_IDLE_EN     (0x1 << 0x3)
+
+void uart_soft_reset(void)
+{
+       struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+       u32 regval;
+
+       regval = readl(&uart_base->uartsyscfg);
+       regval |= UART_RESET;
+       writel(regval, &uart_base->uartsyscfg);
+       while ((readl(&uart_base->uartsyssts) &
+               UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+               ;
+
+       /* Disable smart idle */
+       regval = readl(&uart_base->uartsyscfg);
+       regval |= UART_SMART_IDLE_EN;
+       writel(regval, &uart_base->uartsyscfg);
+}
+#endif