/*
* clock.c
*
- * clocks for AM33XX based boards
+ * Clock initialization for AM33XX boards.
+ * Derived from OMAP4 boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
-#define PRCM_MOD_EN 0x2
-#define PRCM_FORCE_WAKEUP 0x2
-#define PRCM_FUNCTL 0x0
-
-#define PRCM_EMIF_CLK_ACTIVITY BIT(2)
-#define PRCM_L3_GCLK_ACTIVITY BIT(4)
-
-#define PLL_BYPASS_MODE 0x4
-#define ST_MN_BYPASS 0x00000100
-#define ST_DPLL_CLK 0x00000001
-#define CLK_SEL_MASK 0x7ffff
-#define CLK_DIV_MASK 0x1f
-#define CLK_DIV2_MASK 0x7f
-#define CLK_SEL_SHIFT 0x8
-#define CLK_MODE_SEL 0x7
-#define CLK_MODE_MASK 0xfffffff8
-#define CLK_DIV_SEL 0xFFFFFFE0
-#define CPGMAC0_IDLE 0x30000
-#define DPLL_CLKDCOLDO_GATE_CTRL 0x300
-
-const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
-const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
-const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
-
-static void enable_interface_clocks(void)
+static void setup_post_dividers(const struct dpll_regs *dpll_regs,
+ const struct dpll_params *params)
{
- /* Enable all the Interconnect Modules */
- writel(PRCM_MOD_EN, &cmper->l3clkctrl);
- while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
- ;
-
- writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
- while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
- ;
-
- writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
- while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
- ;
-
- writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
- while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
- ;
-
- writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
- while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
- ;
-
- writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
- while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
- ;
-
- writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
- while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
- ;
+ /* Setup post-dividers */
+ if (params->m2 >= 0)
+ writel(params->m2, dpll_regs->cm_div_m2_dpll);
+ if (params->m3 >= 0)
+ writel(params->m3, dpll_regs->cm_div_m3_dpll);
+ if (params->m4 >= 0)
+ writel(params->m4, dpll_regs->cm_div_m4_dpll);
+ if (params->m5 >= 0)
+ writel(params->m5, dpll_regs->cm_div_m5_dpll);
+ if (params->m6 >= 0)
+ writel(params->m6, dpll_regs->cm_div_m6_dpll);
}
-/*
- * Force power domain wake up transition
- * Ensure that the corresponding interface clock is active before
- * using the peripheral
- */
-static void power_domain_wkup_transition(void)
+static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
{
- writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
- writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
- writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
- writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
- writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
+ clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
}
-/*
- * Enable the peripheral clock for required peripherals
- */
-static void enable_per_clocks(void)
+static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
{
- /* Enable the control module though RBL would have done it*/
- writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
- while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
- ;
-
- /* Enable the module clock */
- writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
- while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
- ;
-
- /* Select the Master osc 24 MHZ as Timer2 clock source */
- writel(0x1, &cmdpll->clktimer2clk);
-
- /* UART0 */
- writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
- while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
- ;
-
- /* UART1 */
-#ifdef CONFIG_SERIAL2
- writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
- while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
- ;
-#endif /* CONFIG_SERIAL2 */
-
- /* UART2 */
-#ifdef CONFIG_SERIAL3
- writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
- while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
- ;
-#endif /* CONFIG_SERIAL3 */
-
- /* UART3 */
-#ifdef CONFIG_SERIAL4
- writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
- while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
- ;
-#endif /* CONFIG_SERIAL4 */
-
- /* UART4 */
-#ifdef CONFIG_SERIAL5
- writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
- while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
- ;
-#endif /* CONFIG_SERIAL5 */
-
- /* UART5 */
-#ifdef CONFIG_SERIAL6
- writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
- while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
- ;
-#endif /* CONFIG_SERIAL6 */
-
- /* GPMC */
- writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
- while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
- ;
-
- /* ELM */
- writel(PRCM_MOD_EN, &cmper->elmclkctrl);
- while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
- ;
-
- /* MMC0*/
- writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
- while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
- ;
-
- /* i2c0 */
- writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
- while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
- ;
-
- /* gpio1 module */
- writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
- while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
- ;
-
- /* gpio2 module */
- writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
- while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
- ;
-
- /* gpio3 module */
- writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
- while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
- ;
-
- /* i2c1 */
- writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
- while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
- ;
-
- /* Ethernet */
- writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
- while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
- ;
-
- /* spi0 */
- writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
- while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
- ;
-
- /* RTC */
- writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
- while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
- ;
-
- /* MUSB */
- writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
- while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
- ;
+ if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+ (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+ printf("DPLL locking failed for 0x%x\n",
+ dpll_regs->cm_clkmode_dpll);
+ hang();
+ }
}
-static void mpu_pll_config(void)
+static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
{
- u32 clkmode, clksel, div_m2;
-
- clkmode = readl(&cmwkup->clkmoddpllmpu);
- clksel = readl(&cmwkup->clkseldpllmpu);
- div_m2 = readl(&cmwkup->divm2dpllmpu);
-
- /* Set the PLL to bypass Mode */
- writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
- while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
- ;
-
- clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
- writel(clksel, &cmwkup->clkseldpllmpu);
-
- div_m2 = div_m2 & ~CLK_DIV_MASK;
- div_m2 = div_m2 | MPUPLL_M2;
- writel(div_m2, &cmwkup->divm2dpllmpu);
-
- clkmode = clkmode | CLK_MODE_SEL;
- writel(clkmode, &cmwkup->clkmoddpllmpu);
-
- while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
- ;
+ clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
}
-static void core_pll_config(void)
+static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
{
- u32 clkmode, clksel, div_m4, div_m5, div_m6;
-
- clkmode = readl(&cmwkup->clkmoddpllcore);
- clksel = readl(&cmwkup->clkseldpllcore);
- div_m4 = readl(&cmwkup->divm4dpllcore);
- div_m5 = readl(&cmwkup->divm5dpllcore);
- div_m6 = readl(&cmwkup->divm6dpllcore);
-
- /* Set the PLL to bypass Mode */
- writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
-
- while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
- ;
-
- clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
- writel(clksel, &cmwkup->clkseldpllcore);
-
- div_m4 = div_m4 & ~CLK_DIV_MASK;
- div_m4 = div_m4 | COREPLL_M4;
- writel(div_m4, &cmwkup->divm4dpllcore);
-
- div_m5 = div_m5 & ~CLK_DIV_MASK;
- div_m5 = div_m5 | COREPLL_M5;
- writel(div_m5, &cmwkup->divm5dpllcore);
-
- div_m6 = div_m6 & ~CLK_DIV_MASK;
- div_m6 = div_m6 | COREPLL_M6;
- writel(div_m6, &cmwkup->divm6dpllcore);
-
- clkmode = clkmode | CLK_MODE_SEL;
- writel(clkmode, &cmwkup->clkmoddpllcore);
+ if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
+ (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+ printf("Bypassing DPLL failed 0x%x\n",
+ dpll_regs->cm_clkmode_dpll);
+ }
+}
- while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
- ;
+static void bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+ do_bypass_dpll(dpll_regs);
+ wait_for_bypass(dpll_regs);
}
-static void per_pll_config(void)
+void do_setup_dpll(const struct dpll_regs *dpll_regs,
+ const struct dpll_params *params)
{
- u32 clkmode, clksel, div_m2;
+ u32 temp;
- clkmode = readl(&cmwkup->clkmoddpllper);
- clksel = readl(&cmwkup->clkseldpllper);
- div_m2 = readl(&cmwkup->divm2dpllper);
+ if (!params)
+ return;
- /* Set the PLL to bypass Mode */
- writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
+ temp = readl(dpll_regs->cm_clksel_dpll);
- while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
- ;
+ bypass_dpll(dpll_regs);
- clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
- writel(clksel, &cmwkup->clkseldpllper);
+ /* Set M & N */
+ temp &= ~CM_CLKSEL_DPLL_M_MASK;
+ temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
- div_m2 = div_m2 & ~CLK_DIV2_MASK;
- div_m2 = div_m2 | PERPLL_M2;
- writel(div_m2, &cmwkup->divm2dpllper);
+ temp &= ~CM_CLKSEL_DPLL_N_MASK;
+ temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
- clkmode = clkmode | CLK_MODE_SEL;
- writel(clkmode, &cmwkup->clkmoddpllper);
+ writel(temp, dpll_regs->cm_clksel_dpll);
- while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
- ;
+ setup_post_dividers(dpll_regs, params);
- writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
+ /* Wait till the DPLL locks */
+ do_lock_dpll(dpll_regs);
+ wait_for_lock(dpll_regs);
}
-void ddr_pll_config(unsigned int ddrpll_m)
+static void setup_dplls(void)
{
- u32 clkmode, clksel, div_m2;
+ const struct dpll_params *params;
- clkmode = readl(&cmwkup->clkmoddpllddr);
- clksel = readl(&cmwkup->clkseldpllddr);
- div_m2 = readl(&cmwkup->divm2dpllddr);
+ params = get_dpll_core_params();
+ do_setup_dpll(&dpll_core_regs, params);
- /* Set the PLL to bypass Mode */
- clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
- writel(clkmode, &cmwkup->clkmoddpllddr);
+ params = get_dpll_mpu_params();
+ do_setup_dpll(&dpll_mpu_regs, params);
- /* Wait till bypass mode is enabled */
- while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
- != ST_MN_BYPASS)
- ;
+ params = get_dpll_per_params();
+ do_setup_dpll(&dpll_per_regs, params);
+ writel(0x300, &cmwkup->clkdcoldodpllper);
- clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
- writel(clksel, &cmwkup->clkseldpllddr);
+ params = get_dpll_ddr_params();
+ do_setup_dpll(&dpll_ddr_regs, params);
+}
- div_m2 = div_m2 & CLK_DIV_SEL;
- div_m2 = div_m2 | DDRPLL_M2;
- writel(div_m2, &cmwkup->divm2dpllddr);
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+ u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+ u32 bound = LDELAY;
+
+ while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+ (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+ clkctrl = readl(clkctrl_addr);
+ idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+ MODULE_CLKCTRL_IDLEST_SHIFT;
+ if (--bound == 0) {
+ printf("Clock enable failed for 0x%p idlest 0x%x\n",
+ clkctrl_addr, clkctrl);
+ return;
+ }
+ }
+}
- clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
- writel(clkmode, &cmwkup->clkmoddpllddr);
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+ u32 wait_for_enable)
+{
+ clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+ enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ debug("Enable clock module - %p\n", clkctrl_addr);
+ if (wait_for_enable)
+ wait_for_clk_enable(clkctrl_addr);
+}
- /* Wait till dpll is locked */
- while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
- ;
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+ clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+ enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+ debug("Enable clock domain - %p\n", clkctrl_reg);
}
-void enable_emif_clocks(void)
+void do_enable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
{
- /* Enable the EMIF_FW Functional clock */
- writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
- /* Enable EMIF0 Clock */
- writel(PRCM_MOD_EN, &cmper->emifclkctrl);
- /* Poll if module is functional */
- while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
- ;
+ u32 i, max = 100;
+
+ /* Put the clock domains in SW_WKUP mode */
+ for (i = 0; (i < max) && clk_domains[i]; i++) {
+ enable_clock_domain(clk_domains[i],
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+ }
+
+ /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+ for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+ enable_clock_module(clk_modules_explicit_en[i],
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+ wait_for_enable);
+ };
}
/*
- * Configure the PLL/PRCM for necessary peripherals
+ * Before scaling up the clocks we need to have the PMIC scale up the
+ * voltages first. This will be dependent on which PMIC is in use
+ * and in some cases we may not be scaling things up at all and thus not
+ * need to do anything here.
*/
-void pll_init()
+__weak void scale_vcores(void)
{
- mpu_pll_config();
- core_pll_config();
- per_pll_config();
-
- /* Enable the required interconnect clocks */
- enable_interface_clocks();
-
- /* Power domain wake up transition */
- power_domain_wkup_transition();
+}
- /* Enable the required peripherals */
- enable_per_clocks();
+void prcm_init()
+{
+ enable_basic_clocks();
+ scale_vcores();
+ setup_dplls();
}
projects / karo-tx-uboot.git / blobdiff