arm: am43xx: enable spi clock

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / am33xx / clock_am43xx.c

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index d0bc2340c83511a69316d0acd0ea5dc99c9e7ca6..b6396942bbff5135d3224271d40f2f36f4d54237 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -53,6 +53,8 @@ const struct dpll_regs dpll_ddr_regs = {
 
 void setup_clocks_for_console(void)
 {
+       u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+
        /* Do not add any spl_debug prints in this function */
        clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
                        CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
@@ -63,6 +65,13 @@ void setup_clocks_for_console(void)
                        MODULE_CLKCTRL_MODULEMODE_MASK,
                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+       while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+               (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+               clkctrl = readl(&cmwkup->wkup_uart0ctrl);
+               idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+                        MODULE_CLKCTRL_IDLEST_SHIFT;
+       }
 }
 
 void enable_basic_clocks(void)
@@ -102,11 +111,27 @@ void enable_basic_clocks(void)
                &cmper->emifclkctrl,
                &cmper->otfaemifclkctrl,
                &cmper->qspiclkctrl,
+               &cmper->usb0clkctrl,
+               &cmper->usbphyocp2scp0clkctrl,
+               &cmper->usb1clkctrl,
+               &cmper->usbphyocp2scp1clkctrl,
+               &cmper->spi0clkctrl,
                0
        };
 
+       setbits_le32(&cmper->usb0clkctrl,
+                    USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+       setbits_le32(&cmwkup->usbphy0clkctrl,
+                    USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
+       setbits_le32(&cmper->usb1clkctrl,
+                    USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+       setbits_le32(&cmwkup->usbphy1clkctrl,
+                    USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
        do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 
        /* Select the Master osc clk as Timer2 clock source */
        writel(0x1, &cmdpll->clktimer2clk);
+
+       /* For OPP100 the mac clock should be /5. */
+       writel(0x4, &cmdpll->clkselmacclk);
 }