am33xx: Update DT files, add am335x_gp_evm_config target

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / am33xx / clock_ti814x.c

diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index 8b2878d4ff157fb9a64382954e00073b61ba4644..9b5a47b01892f36c239638d857c0499e8a49f331 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -5,15 +5,7 @@
  *
  * Copyright (C) 2013, Texas Instruments, Incorporated
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -108,103 +100,8 @@ struct ad_pll {
 
 #define OSC_SRC_CTRL                   (PLL_SUBSYS_BASE + 0x2C0)
 
-/* PRCM */
 #define ENET_CLKCTRL_CMPL              0x30000
 
-#define CM_DEFAULT_BASE                        (PRCM_BASE + 0x0500)
-
-struct cm_def {
-       unsigned int resv0[2];
-       unsigned int l3fastclkstctrl;
-       unsigned int resv1[1];
-       unsigned int pciclkstctrl;
-       unsigned int resv2[1];
-       unsigned int ducaticlkstctrl;
-       unsigned int resv3[1];
-       unsigned int emif0clkctrl;
-       unsigned int emif1clkctrl;
-       unsigned int dmmclkctrl;
-       unsigned int fwclkctrl;
-       unsigned int resv4[10];
-       unsigned int usbclkctrl;
-       unsigned int resv5[1];
-       unsigned int sataclkctrl;
-       unsigned int resv6[4];
-       unsigned int ducaticlkctrl;
-       unsigned int pciclkctrl;
-};
-
-#define CM_ALWON_BASE                  (PRCM_BASE + 0x1400)
-
-struct cm_alwon {
-       unsigned int l3slowclkstctrl;
-       unsigned int ethclkstctrl;
-       unsigned int l3medclkstctrl;
-       unsigned int mmu_clkstctrl;
-       unsigned int mmucfg_clkstctrl;
-       unsigned int ocmc0clkstctrl;
-       unsigned int vcpclkstctrl;
-       unsigned int mpuclkstctrl;
-       unsigned int sysclk4clkstctrl;
-       unsigned int sysclk5clkstctrl;
-       unsigned int sysclk6clkstctrl;
-       unsigned int rtcclkstctrl;
-       unsigned int l3fastclkstctrl;
-       unsigned int resv0[67];
-       unsigned int mcasp0clkctrl;
-       unsigned int mcasp1clkctrl;
-       unsigned int mcasp2clkctrl;
-       unsigned int mcbspclkctrl;
-       unsigned int uart0clkctrl;
-       unsigned int uart1clkctrl;
-       unsigned int uart2clkctrl;
-       unsigned int gpio0clkctrl;
-       unsigned int gpio1clkctrl;
-       unsigned int i2c0clkctrl;
-       unsigned int i2c1clkctrl;
-       unsigned int mcasp345clkctrl;
-       unsigned int atlclkctrl;
-       unsigned int mlbclkctrl;
-       unsigned int pataclkctrl;
-       unsigned int resv1[1];
-       unsigned int uart3clkctrl;
-       unsigned int uart4clkctrl;
-       unsigned int uart5clkctrl;
-       unsigned int wdtimerclkctrl;
-       unsigned int spiclkctrl;
-       unsigned int mailboxclkctrl;
-       unsigned int spinboxclkctrl;
-       unsigned int mmudataclkctrl;
-       unsigned int resv2[2];
-       unsigned int mmucfgclkctrl;
-       unsigned int resv3[2];
-       unsigned int ocmc0clkctrl;
-       unsigned int vcpclkctrl;
-       unsigned int resv4[2];
-       unsigned int controlclkctrl;
-       unsigned int resv5[2];
-       unsigned int gpmcclkctrl;
-       unsigned int ethernet0clkctrl;
-       unsigned int ethernet1clkctrl;
-       unsigned int mpuclkctrl;
-       unsigned int debugssclkctrl;
-       unsigned int l3clkctrl;
-       unsigned int l4hsclkctrl;
-       unsigned int l4lsclkctrl;
-       unsigned int rtcclkctrl;
-       unsigned int tpccclkctrl;
-       unsigned int tptc0clkctrl;
-       unsigned int tptc1clkctrl;
-       unsigned int tptc2clkctrl;
-       unsigned int tptc3clkctrl;
-       unsigned int resv7[4];
-       unsigned int dcan01clkctrl;
-       unsigned int mmchs0clkctrl;
-       unsigned int mmchs1clkctrl;
-       unsigned int mmchs2clkctrl;
-       unsigned int custefuseclkctrl;
-};
-
 #define SATA_PLL_BASE                  (CTRL_BASE + 0x0720)
 
 struct sata_pll {
@@ -272,11 +169,6 @@ const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
  */
 static void enable_per_clocks(void)
 {
-       /* UART0 */
-       writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
-       while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
-               ;
-
        /* HSMMC1 */
        writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
        while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
@@ -290,6 +182,12 @@ static void enable_per_clocks(void)
        writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
        while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
                ;
+
+       /* RTC clocks */
+       writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
+       writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
+       while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
+               ;
 }
 
 /*
@@ -313,11 +211,8 @@ static u32 pll_dco_freq_sel(u32 clkout_dco)
 static u32 pll_sigma_delta_val(u32 clkout_dco)
 {
        u32 sig_val = 0;
-       float frac_div;
 
-       frac_div = (float) clkout_dco / 250;
-       frac_div = frac_div + 0.90;
-       sig_val = (int)frac_div;
+       sig_val = (clkout_dco + 225) / 250;
        sig_val = sig_val << 24;
 
        return sig_val;
@@ -463,8 +358,6 @@ void sata_pll_config(void)
                ;
 }
 
-void enable_emif_clocks(void) {};
-
 void enable_dmm_clocks(void)
 {
        writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
@@ -485,13 +378,19 @@ void enable_dmm_clocks(void)
                ;
 }
 
+void setup_clocks_for_console(void)
+{
+       unlock_pll_control_mmr();
+       /* UART0 */
+       writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
+       while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
+               ;
+}
 /*
  * Configure the PLL/PRCM for necessary peripherals
  */
-void pll_init()
+void prcm_init(void)
 {
-       unlock_pll_control_mmr();
-
        /* Enable the control module */
        writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);