*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
-struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
-struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
-struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
-
int dram_init(void)
{
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ sdram_init();
+#endif
+
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
}
-#ifdef CONFIG_SPL_BUILD
-static const struct ddr_data ddr2_data = {
- .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
- |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
- .datardsratio1 = DDR2_RD_DQS>>2,
- .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
- |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
- .datawdsratio1 = DDR2_WR_DQS>>2,
- .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
- |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
- .datawiratio1 = DDR2_PHY_WRLVL>>2,
- .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
- |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
- .datagiratio1 = DDR2_PHY_GATELVL>>2,
- .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
- |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
- .datafwsratio1 = DDR2_PHY_FIFO_WE>>2,
- .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
- |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
- .datawrsratio1 = DDR2_PHY_WR_DATA>>2,
- .datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr2_cmd_ctrl_data = {
- .cmd0csratio = DDR2_RATIO,
- .cmd0csforce = CMD_FORCE,
- .cmd0csdelay = CMD_DELAY,
- .cmd0dldiff = DDR2_DLL_LOCK_DIFF,
- .cmd0iclkout = DDR2_INVERT_CLKOUT,
-
- .cmd1csratio = DDR2_RATIO,
- .cmd1csforce = CMD_FORCE,
- .cmd1csdelay = CMD_DELAY,
- .cmd1dldiff = DDR2_DLL_LOCK_DIFF,
- .cmd1iclkout = DDR2_INVERT_CLKOUT,
-
- .cmd2csratio = DDR2_RATIO,
- .cmd2csforce = CMD_FORCE,
- .cmd2csdelay = CMD_DELAY,
- .cmd2dldiff = DDR2_DLL_LOCK_DIFF,
- .cmd2iclkout = DDR2_INVERT_CLKOUT,
-};
-
-static void config_vtp(void)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_TI81XX
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+ (struct dmm_lisa_map_regs *)DMM_BASE;
+#endif
+#ifndef CONFIG_TI816X
+static struct vtp_reg *vtpreg[2] = {
+ (struct vtp_reg *)VTP0_CTRL_ADDR,
+ (struct vtp_reg *)VTP1_CTRL_ADDR};
+#endif
+#ifdef CONFIG_AM33XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+#endif
+#ifdef CONFIG_AM43XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+static struct cm_device_inst *cm_device =
+ (struct cm_device_inst *)CM_DEVICE_INST;
+#endif
+
+#ifdef CONFIG_TI81XX
+void config_dmm(const struct dmm_lisa_map_regs *regs)
+{
+ enable_dmm_clocks();
+
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+ writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
+ writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
+ writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
+ writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
+}
+#endif
+
+#ifndef CONFIG_TI816X
+static void config_vtp(int nr)
{
- writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
- &vtpreg->vtp0ctrlreg);
- writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
- &vtpreg->vtp0ctrlreg);
- writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
- &vtpreg->vtp0ctrlreg);
+ writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
+ &vtpreg[nr]->vtp0ctrlreg);
+ writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+ &vtpreg[nr]->vtp0ctrlreg);
+ writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
+ &vtpreg[nr]->vtp0ctrlreg);
/* Poll for READY */
- while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
+ while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
VTP_CTRL_READY)
;
}
+#endif
-static void config_emif_ddr2(void)
+void __weak ddr_pll_config(unsigned int ddrpll_m)
{
- int ret;
- struct sdram_config cfg;
- struct sdram_timing tmg;
- struct ddr_phy_control phyc;
-
- /* Program EMIF0 CFG Registers */
- phyc.reg = DDR2_EMIF_READ_LATENCY;
- phyc.reg_sh = DDR2_EMIF_READ_LATENCY;
- phyc.reg2 = DDR2_EMIF_READ_LATENCY;
-
- tmg.time1 = DDR2_EMIF_TIM1;
- tmg.time1_sh = DDR2_EMIF_TIM1;
- tmg.time2 = DDR2_EMIF_TIM2;
- tmg.time2_sh = DDR2_EMIF_TIM2;
- tmg.time3 = DDR2_EMIF_TIM3;
- tmg.time3_sh = DDR2_EMIF_TIM3;
-
- cfg.sdrcr = DDR2_EMIF_SDCFG;
- cfg.sdrcr2 = DDR2_EMIF_SDCFG;
- cfg.refresh = DDR2_EMIF_SDREF;
- cfg.refresh_sh = DDR2_EMIF_SDREF;
-
- /* Program EMIF instance */
- ret = config_ddr_phy(&phyc);
- if (ret < 0)
- printf("Couldn't configure phyc\n");
-
-
- ret = set_sdram_timings(&tmg);
- if (ret < 0)
- printf("Couldn't configure timings\n");
-
- ret = config_sdram(&cfg);
- if (ret < 0)
- printf("Couldn't configure SDRAM\n");
}
-void config_ddr(short ddr_type)
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
+ const struct ddr_data *data, const struct cmd_control *ctrl,
+ const struct emif_regs *regs, int nr)
{
- struct ddr_ioctrl ioctrl;
-
- enable_emif_clocks();
-
- if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
- ddr_pll_config(266);
- config_vtp();
+ ddr_pll_config(pll);
+#ifndef CONFIG_TI816X
+ config_vtp(nr);
+#endif
+ config_cmd_ctrl(ctrl, nr);
- config_cmd_ctrl(&ddr2_cmd_ctrl_data);
+ config_ddr_data(data, nr);
+#ifdef CONFIG_AM33XX
+ config_io_ctrl(ioregs);
- config_ddr_data(0, &ddr2_data);
- config_ddr_data(1, &ddr2_data);
+ /* Set CKE to be controlled by EMIF/DDR PHY */
+ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
- writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
- writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
+#endif
+#ifdef CONFIG_AM43XX
+ writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
+ while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
+ ;
- ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE;
- ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE;
- ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE;
- ioctrl.data1ctl = DDR2_IOCTRL_VALUE;
- ioctrl.data2ctl = DDR2_IOCTRL_VALUE;
+ config_io_ctrl(ioregs);
- config_io_ctrl(&ioctrl);
+ /* Set CKE to be controlled by EMIF/DDR PHY */
+ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
- writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff,
- &ddrctrl->ddrioctrl);
- writel(readl(&ddrctrl->ddrckectrl) | 0x00000001,
- &ddrctrl->ddrckectrl);
+ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+ /* Allow EMIF to control DDR_RESET */
+ writel(0x00000000, &ddrctrl->ddrioctrl);
+#endif
- config_emif_ddr2();
- }
+ /* Program EMIF instance */
+ config_ddr_phy(regs, nr);
+ set_sdram_timings(regs, nr);
+ if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
+ config_sdram_emif4d5(regs, nr);
+ else
+ config_sdram(regs, nr);
}
#endif
projects / karo-tx-uboot.git / blobdiff