/*
- * DDR Configuration for AM33xx devices.
+ * emif4.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * AM33XX emif4 configuration file
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
- * This program is distributed .as is. WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
+#include <asm/emif.h>
-/**
- * Base address for EMIF instances
- */
-static struct emif_regs *emif_reg = {
- (struct emif_regs *)EMIF4_0_CFG_BASE};
-
-/**
- * Base address for DDR instance
- */
-static struct ddr_regs *ddr_reg[2] = {
- (struct ddr_regs *)DDR_PHY_BASE_ADDR,
- (struct ddr_regs *)DDR_PHY_BASE_ADDR2};
-
-/**
- * Base address for ddr io control instances
- */
-static struct ddr_cmdtctrl *ioctrl_reg = {
- (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
-
-/**
- * As a convention, all functions here return 0 on success
- * -1 on failure.
- */
+DECLARE_GLOBAL_DATA_PTR;
-/**
- * Configure SDRAM
- */
-int config_sdram(struct sdram_config *cfg)
+int dram_init(void)
{
- writel(cfg->sdrcr, &emif_reg->sdrcr);
- writel(cfg->sdrcr2, &emif_reg->sdrcr2);
- writel(cfg->refresh, &emif_reg->sdrrcr);
- writel(cfg->refresh_sh, &emif_reg->sdrrcsr);
-
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ sdram_init();
+#endif
+
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
-/**
- * Set SDRAM timings
- */
-int set_sdram_timings(struct sdram_timing *t)
+void dram_init_banksize(void)
{
- writel(t->time1, &emif_reg->sdrtim1);
- writel(t->time1_sh, &emif_reg->sdrtim1sr);
- writel(t->time2, &emif_reg->sdrtim2);
- writel(t->time2_sh, &emif_reg->sdrtim2sr);
- writel(t->time3, &emif_reg->sdrtim3);
- writel(t->time3_sh, &emif_reg->sdrtim3sr);
-
- return 0;
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
}
-/**
- * Configure DDR PHY
- */
-int config_ddr_phy(struct ddr_phy_control *p)
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_TI81XX
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+ (struct dmm_lisa_map_regs *)DMM_BASE;
+#endif
+#ifndef CONFIG_TI816X
+static struct vtp_reg *vtpreg[2] = {
+ (struct vtp_reg *)VTP0_CTRL_ADDR,
+ (struct vtp_reg *)VTP1_CTRL_ADDR};
+#endif
+#ifdef CONFIG_AM33XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+#endif
+#ifdef CONFIG_AM43XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+static struct cm_device_inst *cm_device =
+ (struct cm_device_inst *)CM_DEVICE_INST;
+#endif
+
+#ifdef CONFIG_TI81XX
+void config_dmm(const struct dmm_lisa_map_regs *regs)
{
- writel(p->reg, &emif_reg->ddrphycr);
- writel(p->reg_sh, &emif_reg->ddrphycsr);
+ enable_dmm_clocks();
- return 0;
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+ writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
+ writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
+ writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
+ writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
}
+#endif
-/**
- * Configure DDR CMD control registers
- */
-int config_cmd_ctrl(struct cmd_control *cmd)
+#ifndef CONFIG_TI816X
+static void config_vtp(int nr)
{
- writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
- writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
- writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
- writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
- writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
-
- writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
- writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
- writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
- writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
- writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
-
- writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
- writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
- writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
- writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
- writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
-
- return 0;
+ writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
+ &vtpreg[nr]->vtp0ctrlreg);
+ writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+ &vtpreg[nr]->vtp0ctrlreg);
+ writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
+ &vtpreg[nr]->vtp0ctrlreg);
+
+ /* Poll for READY */
+ while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
+ VTP_CTRL_READY)
+ ;
}
+#endif
-/**
- * Configure DDR DATA registers
- */
-int config_ddr_data(int macrono, struct ddr_data *data)
+void __weak ddr_pll_config(unsigned int ddrpll_m)
{
- writel(data->datardsratio0, &ddr_reg[macrono]->dt0.rdsratio0);
- writel(data->datardsratio1, &ddr_reg[macrono]->dt0.rdsratio1);
-
- writel(data->datawdsratio0, &ddr_reg[macrono]->dt0.wdsratio0);
- writel(data->datawdsratio1, &ddr_reg[macrono]->dt0.wdsratio1);
-
- writel(data->datawiratio0, &ddr_reg[macrono]->dt0.wiratio0);
- writel(data->datawiratio1, &ddr_reg[macrono]->dt0.wiratio1);
-
- writel(data->datagiratio0, &ddr_reg[macrono]->dt0.giratio0);
- writel(data->datagiratio1, &ddr_reg[macrono]->dt0.giratio1);
-
- writel(data->datafwsratio0, &ddr_reg[macrono]->dt0.fwsratio0);
- writel(data->datafwsratio1, &ddr_reg[macrono]->dt0.fwsratio1);
-
- writel(data->datawrsratio0, &ddr_reg[macrono]->dt0.wrsratio0);
- writel(data->datawrsratio1, &ddr_reg[macrono]->dt0.wrsratio1);
-
- writel(data->datadldiff0, &ddr_reg[macrono]->dt0.dldiff0);
-
- return 0;
}
-int config_io_ctrl(struct ddr_ioctrl *ioctrl)
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
+ const struct ddr_data *data, const struct cmd_control *ctrl,
+ const struct emif_regs *regs, int nr)
{
- writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
- writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
- writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
- writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
- writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
-
- return 0;
+ ddr_pll_config(pll);
+#ifndef CONFIG_TI816X
+ config_vtp(nr);
+#endif
+ config_cmd_ctrl(ctrl, nr);
+
+ config_ddr_data(data, nr);
+#ifdef CONFIG_AM33XX
+ config_io_ctrl(ioregs);
+
+ /* Set CKE to be controlled by EMIF/DDR PHY */
+ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+
+#endif
+#ifdef CONFIG_AM43XX
+ writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
+ while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
+ ;
+
+ config_io_ctrl(ioregs);
+
+ /* Set CKE to be controlled by EMIF/DDR PHY */
+ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+
+ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+ /* Allow EMIF to control DDR_RESET */
+ writel(0x00000000, &ddrctrl->ddrioctrl);
+#endif
+
+ /* Program EMIF instance */
+ config_ddr_phy(regs, nr);
+ set_sdram_timings(regs, nr);
+ if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
+ config_sdram_emif4d5(regs, nr);
+ else
+ config_sdram(regs, nr);
}
+#endif
projects / karo-tx-uboot.git / blobdiff