}
}
/* DSB to make sure the operation is complete */
- CP15DSB;
+ DSB;
}
static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
}
}
/* DSB to make sure the operation is complete */
- CP15DSB;
+ DSB;
}
static void v7_maint_dcache_level_setway(u32 level, u32 operation)
}
/* DSB to make sure the operation is complete */
- CP15DSB;
+ DSB;
}
/* Invalidate TLB */
static void v7_inval_tlb(void)
{
- /* Invalidate entire unified TLB */
- asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
- /* Invalidate entire data TLB */
- asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
- /* Invalidate entire instruction TLB */
- asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
+ asm volatile (
+ /* Invalidate entire unified TLB */
+ "mcr p15, 0, %0, c8, c7, 0\n"
+ /* Invalidate entire data TLB */
+ "mcr p15, 0, %0, c8, c6, 0\n"
+ /* Invalidate entire instruction TLB */
+ "mcr p15, 0, %0, c8, c5, 0\n"
+ : : "r" (0));
/* Full system DSB - make sure that the invalidation is complete */
- CP15DSB;
+ DSB;
/* Full system ISB - make sure the instruction stream sees it */
- CP15ISB;
+ ISB;
}
void invalidate_dcache_all(void)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
- /*
- * Invalidate all instruction caches to PoU.
- * Also flushes branch target cache.
- */
- asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
+ asm volatile (
+ /*
+ * Invalidate all instruction caches to PoU.
+ * Also flushes branch target cache.
+ */
+ "mcr p15, 0, %0, c7, c5, 0\n"
+
+ /* Invalidate entire branch predictor array */
+ "mcr p15, 0, %0, c7, c5, 6\n"
- /* Invalidate entire branch predictor array */
- asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
+ : : "r" (0));
/* Full system DSB - make sure that the invalidation is complete */
- CP15DSB;
+ DSB;
/* ISB - make sure the instruction stream sees it */
- CP15ISB;
+ ISB;
}
#else
void invalidate_icache_all(void)