TX6 Release 2013-04-22

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx5 / clock.c

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 76c2c529a88fb72e7a5f96e9497725b48e1f6646..bb51b8278c9fd9d9195be3f2af3c8dcbc1d3fec4 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -89,6 +89,35 @@ struct pll_param {
 
 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 
+int clk_enable(struct clk *clk)
+{
+       int ret = 0;
+
+       if (!clk)
+               return 0;
+       if (clk->usecount++ == 0) {
+               ret = clk->enable(clk);
+               if (ret)
+                       clk->usecount--;
+       }
+       return ret;
+}
+
+void clk_disable(struct clk *clk)
+{
+       if (!clk)
+               return;
+
+       if (!(--clk->usecount)) {
+               if (clk->disable)
+                       clk->disable(clk);
+       }
+       if (clk->usecount < 0) {
+               printf("%s: clk %p underflow\n", __func__, clk);
+               hang();
+       }
+}
+
 void set_usboh3_clk(void)
 {
        clrsetbits_le32(&mxc_ccm->cscmr1,
@@ -110,6 +139,34 @@ void enable_usboh3_clk(unsigned char enable)
                        MXC_CCM_CCGR2_USBOH3_60M(cg));
 }
 
+void ipu_clk_enable(void)
+{
+       /* IPU root clock derived from AXI B */
+       clrsetbits_le32(&mxc_ccm->cbcmr, MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK,
+                       MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(1));
+
+       setbits_le32(&mxc_ccm->CCGR5,
+               MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
+
+       /* Handshake with IPU when certain clock rates are changed. */
+       clrbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
+
+       /* Handshake with IPU when LPM is entered as its enabled. */
+       clrbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
+}
+
+void ipu_clk_disable(void)
+{
+       clrbits_le32(&mxc_ccm->CCGR5,
+               MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
+
+       /* Handshake with IPU when certain clock rates are changed. */
+       setbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
+
+       /* Handshake with IPU when LPM is entered as its enabled. */
+       setbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
+}
+
 #ifdef CONFIG_I2C_MXC
 /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
@@ -644,71 +701,63 @@ static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
 
 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
        {       \
-               writel(0x1232, &pll->ctrl);             \
-               writel(0x2, &pll->config);              \
-               writel((((pd) - 1) << 0) | ((fi) << 4), \
-                       &pll->op);                      \
-               writel(fn, &(pll->mfn));                \
-               writel((fd) - 1, &pll->mfd);            \
-               writel((((pd) - 1) << 0) | ((fi) << 4), \
-                       &pll->hfs_op);                  \
-               writel(fn, &pll->hfs_mfn);              \
-               writel((fd) - 1, &pll->hfs_mfd);        \
-               writel(0x1232, &pll->ctrl);             \
-               while (!readl(&pll->ctrl) & 0x1)        \
+               __raw_writel(0x1232, &pll->ctrl);               \
+               __raw_writel(0x2, &pll->config);                \
+               __raw_writel((((pd) - 1) << 0) | ((fi) << 4),   \
+                       &pll->op);                              \
+               __raw_writel(fn, &(pll->mfn));                  \
+               __raw_writel((fd) - 1, &pll->mfd);              \
+               __raw_writel((((pd) - 1) << 0) | ((fi) << 4),   \
+                       &pll->hfs_op);                          \
+               __raw_writel(fn, &pll->hfs_mfn);                \
+               __raw_writel((fd) - 1, &pll->hfs_mfd);          \
+               __raw_writel(0x1232, &pll->ctrl);               \
+               while (!__raw_readl(&pll->ctrl) & 0x1)          \
                        ;\
        }
 
 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
 {
-       u32 ccsr = readl(&mxc_ccm->ccsr);
+       u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
        struct mxc_pll_reg *pll = mxc_plls[index];
 
        switch (index) {
        case PLL1_CLOCK:
                /* Switch ARM to PLL2 clock */
-               writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
-                               &mxc_ccm->ccsr);
+               __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
                CHANGE_PLL_SETTINGS(pll, pll_param->pd,
                                        pll_param->mfi, pll_param->mfn,
                                        pll_param->mfd);
                /* Switch back */
-               writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
-                               &mxc_ccm->ccsr);
+               __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
                break;
        case PLL2_CLOCK:
                /* Switch to pll2 bypass clock */
-               writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
-                               &mxc_ccm->ccsr);
+               __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
                CHANGE_PLL_SETTINGS(pll, pll_param->pd,
                                        pll_param->mfi, pll_param->mfn,
                                        pll_param->mfd);
                /* Switch back */
-               writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
-                               &mxc_ccm->ccsr);
+               __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
                break;
        case PLL3_CLOCK:
                /* Switch to pll3 bypass clock */
-               writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
-                               &mxc_ccm->ccsr);
+               __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
                CHANGE_PLL_SETTINGS(pll, pll_param->pd,
                                        pll_param->mfi, pll_param->mfn,
                                        pll_param->mfd);
                /* Switch back */
-               writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
-                               &mxc_ccm->ccsr);
+               __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
                break;
 #ifdef CONFIG_MX53
        case PLL4_CLOCK:
                /* Switch to pll4 bypass clock */
-               writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
-                               &mxc_ccm->ccsr);
+               __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
                CHANGE_PLL_SETTINGS(pll, pll_param->pd,
                                        pll_param->mfi, pll_param->mfn,
                                        pll_param->mfd);
                /* Switch back */
-               writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
-                               &mxc_ccm->ccsr);
+               __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
                break;
 #endif
        default:
@@ -729,7 +778,9 @@ static int config_core_clk(u32 ref, u32 freq)
        /* The case that periph uses PLL1 is not considered here */
        ret = calc_pll_params(ref, freq, &pll_param);
        if (ret != 0) {
-               printf("Error:Can't find pll parameters: %d\n", ret);
+               printf("Error: Can't find pll parameters for %u.%03uMHz ref %u.%03uMHz\n",
+                       freq / 1000000, freq / 1000 % 1000,
+                       ref / 1000000, ref / 1000 % 1000);
                return ret;
        }