void enable_usboh3_clk(unsigned char enable)
{
- if (enable)
- setbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
- else
- clrbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+ clrsetbits_le32(&mxc_ccm->CCGR2,
+ MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR2_USBOH3_60M(cg));
}
#ifdef CONFIG_I2C_MXC
if (i2c_num > 2)
return -EINVAL;
- mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
+ mask = MXC_CCM_CCGR_CG_MASK <<
+ (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
if (enable)
setbits_le32(&mxc_ccm->CCGR1, mask);
else
void enable_usb_phy1_clk(unsigned char enable)
{
- if (enable)
- setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
- else
- clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+ clrsetbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR4_USB_PHY1(cg));
}
void set_usb_phy2_clk(void)
void enable_usb_phy2_clk(unsigned char enable)
{
- if (enable)
- setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
- else
- clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+ clrsetbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR4_USB_PHY2(cg));
}
/*