/* reconfigure L2 cache aux control reg */
ldr r0, =0xC0 | /* tag RAM */ \
- 0x4 | /* data RAM */ \
- 1 << 24 | /* disable write allocate delay */ \
- 1 << 23 | /* disable write allocate combine */ \
- 1 << 22 /* disable write allocate */
+ 0x4 | /* data RAM */ \
+ 1 << 24 | /* disable write allocate delay */ \
+ 1 << 23 | /* disable write allocate combine */ \
+ 1 << 22 /* disable write allocate */
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)
ldr r3, [r4, #ROM_SI_REV]
cmp r3, #0x10
#endif
mcr 15, 1, r0, c9, c0, 2
+
+ /* enable L2 cache */
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #2
+ mcr 15, 0, r0, c1, c0, 1
+
.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
/* M4IF setup */
.macro init_m4if
-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51
/* VPU and IPU given higher priority (0x4)
* IPU accesses with ID=0x1 given highest priority (=0xA)
*/
.macro init_clock
ldr r0, =CCM_BASE_ADDR
-#if defined (CONFIG_MX51)
+#if defined (CONFIG_SOC_MX51)
/* Gate off clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #CLKCTL_CCOSR]
-#else /* CONFIG_MX53 */
+#else /* CONFIG_SOC_MX53 */
/* Gate off clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
#error Unsupported CONFIG_SYS_CPU_CLK value
#endif
- setup_pll PLL3_BASE_ADDR, 400
+ setup_pll PLL3_BASE_ADDR, 400
#ifndef CONFIG_TX53
- /* Switch peripheral to PLL3 */
- ldr r1, =0x00015154
- str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, =0x02898945
- str r1, [r0, #CLKCTL_CBCDR]
- /* make sure change is effective */
+ /* Switch peripheral to PLL3 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x00015154
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, =0x02898945
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
tst r1, #0x7f
- bne 1b
+ bne 1b
- setup_pll PLL2_BASE_ADDR, 400
+ setup_pll PLL2_BASE_ADDR, 400
/* Switch peripheral to PLL2 */
ldr r1, =0x00888945
tst r1, #0x7f
bne 1b
+ setup_pll PLL3_BASE_ADDR, 216
+
setup_pll PLL4_BASE_ADDR, 455
#else /* CONFIG_TX53 */
str r1, [r0, #CLKCTL_CCGR6]
str r1, [r0, #CLKCTL_CCGR7]
- mov r1, #0x00000
- str r1, [r0, #CLKCTL_CCDR]
-
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
+ mov r1, #0x00000
+ str r1, [r0, #CLKCTL_CCDR]
-#endif /* CONFIG_MX53 */
-.endm
+ /* for cko - for ARM div by 8 */
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
-.macro setup_wdog
- ldr r0, =WDOG1_BASE_ADDR
- mov r1, #0x30
- strh r1, [r0]
+#endif /* CONFIG_SOC_MX53 */
.endm
ENTRY(lowlevel_init)
.word DP_MFD_800
.word DP_MFN_800
#endif
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)
W_DP_665: .word DP_OP_665
.word DP_MFD_665
.word DP_MFN_665