TX6 Release 2013-04-22

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx5 / lowlevel_init.S

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 6d9396a97670d87aad34358129b037fbceb40478..8b95d776301c15136f06e810f6ef557a51479fee 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -206,7 +206,13 @@ setup_pll_func:
        setup_pll PLL1_BASE_ADDR, 864
        setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
 #else
+#if !defined(CONFIG_SYS_CPU_CLK) || CONFIG_SYS_CPU_CLK == 800
        setup_pll PLL1_BASE_ADDR, 800
+#elif CONFIG_SYS_CPU_CLK == 600
+       setup_pll PLL1_BASE_ADDR, 600
+#else
+#error Unsupported CONFIG_SYS_CPU_CLK value
+#endif
 #endif
 
        setup_pll PLL3_BASE_ADDR, 665
@@ -220,7 +226,6 @@ setup_pll_func:
        setup_pll PLL2_BASE_ADDR, 665
 
        /* Switch peripheral to PLL2 */
-       ldr r0, =CCM_BASE_ADDR
        ldr r1, =0x19239145
        str r1, [r0, #CLKCTL_CBCDR]
        ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
@@ -320,7 +325,6 @@ setup_pll_func:
         setup_pll PLL2_BASE_ADDR, 400
 
        /* Switch peripheral to PLL2 */
-       ldr r0, =CCM_BASE_ADDR
        ldr r1, =0x00808145
        orr r1, r1, #(2 << 10)
        orr r1, r1, #(0 << 16)
@@ -332,8 +336,8 @@ setup_pll_func:
 
        /*change uart clk parent to pll2*/
        ldr r1, [r0, #CLKCTL_CSCMR1]
-       and r1, r1, #0xfcffffff
-       orr r1, r1, #0x01000000
+       bic r1, #(0x3 << 24)
+       orr r1, r1, #(0x1 << 24)
        str r1, [r0, #CLKCTL_CSCMR1]
 
        /* make sure change is effective */
@@ -360,9 +364,13 @@ setup_pll_func:
 
        /* make uart div=6 */
        ldr r1, [r0, #CLKCTL_CSCDR1]
-       and r1, r1, #0xffffffc0
+       bic r1, #(0x3f << 0)
        orr r1, r1, #0x0a
        str r1, [r0, #CLKCTL_CSCDR1]
+       /* make sure divider effective */
+1:     ldr r1, [r0, #CLKCTL_CDHIPR]
+       cmp r1, #0x0
+       bne 1b
 
        /* Restore the default values in the Gate registers */
        ldr r1, =0xFFFFFFFF
@@ -434,6 +442,9 @@ W_DP_800:           .word DP_OP_800
 W_DP_665:              .word DP_OP_665
                        .word DP_MFD_665
                        .word DP_MFN_665
+W_DP_600:              .word DP_OP_600
+                       .word DP_MFD_600
+                       .word DP_MFN_600
 #endif
 W_DP_216:              .word DP_OP_216
                        .word DP_MFD_216