remove obsolete functions ocotp_clk_{en,dis}able
[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / clock.c
index 980a6eb..6a51173 100644 (file)
@@ -175,19 +175,32 @@ void enable_usboh3_clk(unsigned char enable)
 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
 void enable_enet_clk(unsigned char enable)
 {
-       u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
+       u32 mask, *addr;
+
+       if (is_cpu_type(MXC_CPU_MX6UL)) {
+               mask = MXC_CCM_CCGR3_ENET_MASK;
+               addr = &imx_ccm->CCGR3;
+       } else {
+               mask = MXC_CCM_CCGR1_ENET_MASK;
+               addr = &imx_ccm->CCGR1;
+       }
 
        if (enable)
-               setbits_le32(&imx_ccm->CCGR1, mask);
+               setbits_le32(addr, mask);
        else
-               clrbits_le32(&imx_ccm->CCGR1, mask);
+               clrbits_le32(addr, mask);
 }
 #endif
 
 #ifdef CONFIG_MXC_UART
 void enable_uart_clk(unsigned char enable)
 {
-       u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
+       u32 mask;
+
+       if (is_cpu_type(MXC_CPU_MX6UL))
+               mask = MXC_CCM_CCGR5_UART_MASK;
+       else
+               mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 
        if (enable)
                setbits_le32(&imx_ccm->CCGR5, mask);
@@ -235,7 +248,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
                        reg &= ~mask;
                __raw_writel(reg, &imx_ccm->CCGR2);
        } else {
-               if (is_cpu_type(MXC_CPU_MX6SX)) {
+               if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
                        mask = MXC_CCM_CCGR6_I2C4_MASK;
                        addr = &imx_ccm->CCGR6;
                } else {
@@ -293,9 +306,9 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
                return infreq * (20 + div * 2);
        case PLL_USBOTG:
                div = __raw_readl(&anatop->usb1_pll_480_ctrl);
-               if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
+               if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
                        return infreq;
-               div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
+               div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 
                return infreq * (20 + div * 2);
        case PLL_AUDIO:
@@ -321,9 +334,9 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
                return 25000000 * (div + (div >> 1) + 1);
        case PLL_USB2:
                div = __raw_readl(&anatop->usb2_pll_480_ctrl);
-               if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
+               if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
                        return infreq;
-               div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
+               div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 
                return infreq * (20 + div * 2);
        case PLL_MLB:
@@ -343,9 +356,11 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 
        switch (pll) {
        case PLL_528:
-               if (pfd_num == 3) {
-                       /* No PFD3 on PLL2 */
-                       return 0;
+               if (!is_cpu_type(MXC_CPU_MX6UL)) {
+                       if (pfd_num == 3) {
+                               /* No PFD3 on PPL2 */
+                               return 0;
+                       }
                }
                div = __raw_readl(&anatop->pfd_528);
                freq = (u64)decode_pll(PLL_528, MXC_HCLK);
@@ -377,10 +392,12 @@ static u32 get_mcu_main_clk(void)
 
 u32 get_periph_clk(void)
 {
-       u32 reg, freq = 0;
+       u32 reg, div = 0, freq = 0;
 
        reg = __raw_readl(&imx_ccm->cbcdr);
        if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+               div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
+                      MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
                reg = __raw_readl(&imx_ccm->cbcmr);
                reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
                reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
@@ -416,7 +433,7 @@ u32 get_periph_clk(void)
                }
        }
 
-       return freq;
+       return freq / (div + 1);
 }
 
 static u32 get_ipg_clk(void)
@@ -435,10 +452,12 @@ static u32 get_ipg_per_clk(void)
        u32 reg, perclk_podf;
 
        reg = __raw_readl(&imx_ccm->cscmr1);
-#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
-       if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
-               return MXC_HCLK; /* OSC 24Mhz */
-#endif
+       if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+           is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+               if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
+                       return MXC_HCLK; /* OSC 24Mhz */
+       }
+
        perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 
        return get_ipg_clk() / (perclk_podf + 1);
@@ -449,10 +468,13 @@ static u32 get_uart_clk(void)
        u32 reg, uart_podf;
        u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
        reg = __raw_readl(&imx_ccm->cscdr1);
-#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
-       if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
-               freq = MXC_HCLK;
-#endif
+
+       if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+           is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+               if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+                       freq = MXC_HCLK;
+       }
+
        reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
        uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 
@@ -464,8 +486,14 @@ static u32 get_cspi_clk(void)
        u32 reg, cspi_podf;
 
        reg = __raw_readl(&imx_ccm->cscdr2);
-       reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
-       cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+       cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
+                    MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+       if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
+           is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+               if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
+                       return MXC_HCLK / (cspi_podf + 1);
+       }
 
        return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }
@@ -473,7 +501,7 @@ static u32 get_cspi_clk(void)
 static u32 get_axi_clk(void)
 {
        u32 root_freq, axi_podf;
-       u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
+       u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 
        axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
        axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
@@ -483,9 +511,9 @@ static u32 get_axi_clk(void)
                        root_freq = mxc_get_pll_pfd(PLL_528, 2);
                else
                        root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
-       } else
+       } else {
                root_freq = get_periph_clk();
-
+       }
        return  root_freq / (axi_podf + 1);
 }
 
@@ -539,6 +567,8 @@ static u32 get_nfc_clk(void)
        case 3:
                root_freq = mxc_get_pll_pfd(PLL_528, 2);
                break;
+       default:
+               return 0;
        }
 
        return root_freq / (pred + 1) / (podf + 1);
@@ -615,47 +645,60 @@ static int set_nfc_clk(u32 ref, u32 freq_khz)
        return 0;
 }
 
-#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 static u32 get_mmdc_ch0_clk(void)
 {
        u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
        u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-       u32 freq, podf;
-
-       podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
-                       >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 
-       switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
-               MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
-       case 0:
-               freq = decode_pll(PLL_528, MXC_HCLK);
-               break;
-       case 1:
-               freq = mxc_get_pll_pfd(PLL_528, 2);
-               break;
-       case 2:
-               freq = mxc_get_pll_pfd(PLL_528, 0);
-               break;
-       case 3:
-               /* static / 2 divider */
-               freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
+       u32 freq, podf, per2_clk2_podf;
+
+       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+           is_cpu_type(MXC_CPU_MX6SL)) {
+               podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
+                       MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+               if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
+                       per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
+                               MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
+                       if (is_cpu_type(MXC_CPU_MX6SL)) {
+                               if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+                                       freq = MXC_HCLK;
+                               else
+                                       freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+                       } else {
+                               if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+                                       freq = decode_pll(PLL_528, MXC_HCLK);
+                               else
+                                       freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+                       }
+               } else {
+                       per2_clk2_podf = 0;
+                       switch ((cbcmr &
+                               MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+                               MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+                       case 0:
+                               freq = decode_pll(PLL_528, MXC_HCLK);
+                               break;
+                       case 1:
+                               freq = mxc_get_pll_pfd(PLL_528, 2);
+                               break;
+                       case 2:
+                               freq = mxc_get_pll_pfd(PLL_528, 0);
+                               break;
+                       case 3:
+                               /* static / 2 divider */
+                               freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
+                               break;
+                       }
+               }
+               return freq / (podf + 1) / (per2_clk2_podf + 1);
+       } else {
+               podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+                       MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+               return get_periph_clk() / (podf + 1);
        }
-
-       return freq / (podf + 1);
-
-}
-#else
-static u32 get_mmdc_ch0_clk(void)
-{
-       u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-       u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
-                               MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
-
-       return get_periph_clk() / (mmdc_ch0_podf + 1);
 }
-#endif
 
-#ifdef CONFIG_SOC_MX6SX
+#ifdef CONFIG_FSL_QSPI
 /* qspi_num can be from 0 - 1 */
 void enable_qspi_clk(int qspi_num)
 {
@@ -816,6 +859,7 @@ u32 imx_get_fecclk(void)
        return mxc_get_clock(MXC_IPG_CLK);
 }
 
+#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 static int enable_enet_pll(uint32_t en)
 {
        u32 reg;
@@ -838,8 +882,9 @@ static int enable_enet_pll(uint32_t en)
        writel(reg, &anatop->pll_enet);
        return 0;
 }
+#endif
 
-#ifndef CONFIG_SOC_MX6SX
+#ifdef CONFIG_CMD_SATA
 static void ungate_sata_clock(void)
 {
        struct mxc_ccm_reg *const imx_ccm =
@@ -848,18 +893,7 @@ static void ungate_sata_clock(void)
        /* Enable SATA clock. */
        setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 }
-#endif
-
-static void ungate_pcie_clock(void)
-{
-       struct mxc_ccm_reg *const imx_ccm =
-               (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-       /* Enable PCIe clock. */
-       setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
-}
 
-#ifndef CONFIG_SOC_MX6SX
 int enable_sata_clock(void)
 {
        ungate_sata_clock();
@@ -875,6 +909,16 @@ void disable_sata_clock(void)
 }
 #endif
 
+#ifdef CONFIG_PCIE_IMX
+static void ungate_pcie_clock(void)
+{
+       struct mxc_ccm_reg *const imx_ccm =
+               (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       /* Enable PCIe clock. */
+       setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
+}
+
 int enable_pcie_clock(void)
 {
        struct anatop_regs *anatop_regs =
@@ -914,7 +958,7 @@ int enable_pcie_clock(void)
        clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 
        /* Party time! Ungate the clock to the PCIe. */
-#ifndef CONFIG_SOC_MX6SX
+#ifdef CONFIG_CMD_SATA
        ungate_sata_clock();
 #endif
        ungate_pcie_clock();
@@ -922,6 +966,7 @@ int enable_pcie_clock(void)
        return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
                               BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 }
+#endif
 
 #ifdef CONFIG_SECURE_BOOT
 void hab_caam_clock_enable(unsigned char enable)
@@ -957,20 +1002,20 @@ static void enable_pll3(void)
 
        /* make sure pll3 is enabled */
        if ((readl(&anatop->usb1_pll_480_ctrl) &
-                       BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) {
+                       BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
                /* enable pll's power */
-               writel(BM_ANADIG_USB_PLL_480_CTRL_POWER,
+               writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
                       &anatop->usb1_pll_480_ctrl_set);
                writel(0x80, &anatop->ana_misc2_clr);
                /* wait for pll lock */
                while ((readl(&anatop->usb1_pll_480_ctrl) &
-                       BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0)
+                       BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
                        ;
                /* disable bypass */
-               writel(BM_ANADIG_USB_PLL_480_CTRL_BYPASS,
+               writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
                       &anatop->usb1_pll_480_ctrl_clr);
                /* enable pll output */
-               writel(BM_ANADIG_USB_PLL_480_CTRL_ENABLE,
+               writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
                       &anatop->usb1_pll_480_ctrl_set);
        }
 }
@@ -1058,20 +1103,6 @@ void ldb_clk_disable(int ldb)
        }
 }
 
-void ocotp_clk_enable(void)
-{
-       u32 reg = readl(&imx_ccm->CCGR2);
-       reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
-       writel(reg, &imx_ccm->CCGR2);
-}
-
-void ocotp_clk_disable(void)
-{
-       u32 reg = readl(&imx_ccm->CCGR2);
-       reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
-       writel(reg, &imx_ccm->CCGR2);
-}
-
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
        switch (clk) {
@@ -1385,6 +1416,11 @@ void enable_ipu_clock(void)
        reg = readl(&mxc_ccm->CCGR3);
        reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
        writel(reg, &mxc_ccm->CCGR3);
+
+       if (is_mx6dqp()) {
+               setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
+               setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
+       }
 }
 #endif
 /***************************************************/