- switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
- case 0:
- freq = decode_pll(PLL_528, MXC_HCLK);
- break;
- case 1:
- freq = mxc_get_pll_pfd(PLL_528, 2);
- break;
- case 2:
- freq = mxc_get_pll_pfd(PLL_528, 0);
- break;
- case 3:
- /* static / 2 divider */
- freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
+ u32 freq, podf, per2_clk2_podf;
+
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+ is_cpu_type(MXC_CPU_MX6SL)) {
+ podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
+ MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+ if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
+ per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
+ MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
+ if (is_cpu_type(MXC_CPU_MX6SL)) {
+ if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+ freq = MXC_HCLK;
+ else
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ } else {
+ if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+ freq = decode_pll(PLL_528, MXC_HCLK);
+ else
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ }
+ } else {
+ per2_clk2_podf = 0;
+ switch ((cbcmr &
+ MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+ MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+ case 0:
+ freq = decode_pll(PLL_528, MXC_HCLK);
+ break;
+ case 1:
+ freq = mxc_get_pll_pfd(PLL_528, 2);
+ break;
+ case 2:
+ freq = mxc_get_pll_pfd(PLL_528, 0);
+ break;
+ case 3:
+ /* static / 2 divider */
+ freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
+ break;
+ }
+ }
+ return freq / (podf + 1) / (per2_clk2_podf + 1);
+ } else {
+ podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+ MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+ return get_periph_clk() / (podf + 1);