#include <asm/io.h>
#include <asm/types.h>
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#if defined(CONFIG_SOC_MX6SX)
+/* Configure MX6SX mmdc iomux */
+void mx6sx_dram_iocfg(unsigned width,
+ const struct mx6sx_iomux_ddr_regs *ddr,
+ const struct mx6sx_iomux_grp_regs *grp)
+{
+ struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
+ struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
+
+ /* DDR IO TYPE */
+ writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
+ writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
+
+ /* CLOCK */
+ writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
+
+ /* ADDRESS */
+ writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
+ writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
+ writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
+
+ /* Control */
+ writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
+ writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
+ writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
+ writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
+ writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
+ writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
+ writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
+
+ /* Data Strobes */
+ writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
+ writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
+ writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
+ if (width >= 32) {
+ writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
+ writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
+ }
+
+ /* Data */
+ writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
+ writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
+ writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
+ if (width >= 32) {
+ writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
+ writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
+ }
+ writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
+ writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
+ if (width >= 32) {
+ writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
+ writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
+ }
+}
+#endif
+
+#ifdef CONFIG_SOC_MX6UL
+void mx6ul_dram_iocfg(unsigned width,
+ const struct mx6ul_iomux_ddr_regs *ddr,
+ const struct mx6ul_iomux_grp_regs *grp)
+{
+ struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
+ struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
+
+ /* DDR IO TYPE */
+ writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
+ writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
+
+ /* CLOCK */
+ writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
+
+ /* ADDRESS */
+ writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
+ writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
+ writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
+
+ /* Control */
+ writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
+ writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
+ writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
+ writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
+ writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
+
+ /* Data Strobes */
+ writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
+ writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
+ writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
+
+ /* Data */
+ writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
+ writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
+ writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
+ writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
+ writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
+}
+#endif
+
+#if defined(CONFIG_SOC_MX6QDL) || defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6D)
/* Configure MX6DQ mmdc iomux */
void mx6dq_dram_iocfg(unsigned width,
const struct mx6dq_iomux_ddr_regs *ddr,
}
#endif
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#if defined(CONFIG_SOC_MX6QDL) || defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
/* Configure MX6SDL mmdc iomux */
void mx6sdl_dram_iocfg(unsigned width,
const struct mx6sdl_iomux_ddr_regs *ddr,
*/
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
+#define MMDC1(entry, value) do { \
+ if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) \
+ mmdc1->entry = value; \
+ } while (0)
+
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,
const struct mx6_ddr3_cfg *ddr3_cfg)
u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
u8 coladdr;
int clkper; /* clock period in picoseconds */
- int clock; /* clock freq in mHz */
+ int clock; /* clock freq in MHz */
int cs;
+ u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
- mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+ if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
+ mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
- /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
+ /* Limit mem_speed for MX6D/MX6Q */
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
- clock = 528;
+ if (mem_speed > 1066)
+ mem_speed = 1066; /* 1066 MT/s */
+
tcwl = 4;
}
- /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
+ /* Limit mem_speed for MX6S/MX6DL */
else {
- clock = 400;
+ if (mem_speed > 800)
+ mem_speed = 800; /* 800 MT/s */
+
tcwl = 3;
}
+
+ clock = mem_speed / 2;
+ /*
+ * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
+ * up to 528 MHz, so reduce the clock to fit chip specs
+ */
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+ if (clock > 528)
+ clock = 528; /* 528 MHz */
+ }
+
clkper = (1000 * 1000) / clock; /* pico seconds */
todtlon = tcwl;
taxpd = tcwl;
}
txpr = txs;
- switch (ddr3_cfg->mem_speed) {
+ switch (mem_speed) {
case 800:
- txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+ txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
+ tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(40000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(50000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
}
break;
case 1066:
- txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
+ txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
+ tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(37500, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(50000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
- }
- break;
- case 1333:
- txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
- if (ddr3_cfg->pagesz == 1) {
- tfaw = DIV_ROUND_UP(30000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
- } else {
- tfaw = DIV_ROUND_UP(45000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
- }
- break;
- case 1600:
- txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3 * clkper, 5000), clkper) - 1;
- if (ddr3_cfg->pagesz == 1) {
- tfaw = DIV_ROUND_UP(30000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
- } else {
- tfaw = DIV_ROUND_UP(40000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
}
break;
default:
hang();
break;
}
- txpdll = DIV_ROUND_UP(MAX(10 * clkper, 24000), clkper) - 1;
- tcksre = DIV_ROUND_UP(MAX(5 * clkper, 10000), clkper);
+ txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
+ tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
taonpd = DIV_ROUND_UP(2000, clkper) - 1;
tcksrx = tcksre;
taofpd = taonpd;
twr = DIV_ROUND_UP(15000, clkper) - 1;
- tmrd = DIV_ROUND_UP(MAX(12 * clkper, 15000), clkper) - 1;
+ tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
- twtr = ROUND(MAX(4 * clkper, 7500) / clkper, 1) - 1;
+ twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
trcd = trp;
trtp = twtr;
cs0_end = 4 * sysinfo->cs_density - 1;
debug("density:%d Gb (%d Gb per chip)\n",
sysinfo->cs_density, ddr3_cfg->density);
debug("clock: %dMHz (%d ps)\n", clock, clkper);
- debug("memspd:%d\n", ddr3_cfg->mem_speed);
+ debug("memspd:%d\n", mem_speed);
debug("tcke=%d\n", tcke);
debug("tcksrx=%d\n", tcksrx);
debug("tcksre=%d\n", tcksre);
mmdc0->mprddlctl = calib->p0_mprddlctl;
mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
if (sysinfo->dsize > 1) {
- mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
- mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
- mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
- mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
- mmdc1->mprddlctl = calib->p1_mprddlctl;
- mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
+ MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
+ MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
+ MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
+ MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
+ MMDC1(mprddlctl, calib->p1_mprddlctl);
+ MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
}
/* Read data DQ Byte0-3 delay */
}
if (sysinfo->dsize > 1) {
- mmdc1->mprddqby0dl = 0x33333333;
- mmdc1->mprddqby1dl = 0x33333333;
- mmdc1->mprddqby2dl = 0x33333333;
- mmdc1->mprddqby3dl = 0x33333333;
+ MMDC1(mprddqby0dl, 0x33333333);
+ MMDC1(mprddqby1dl, 0x33333333);
+ MMDC1(mprddqby2dl, 0x33333333);
+ MMDC1(mprddqby3dl, 0x33333333);
}
/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
mmdc0->mpodtctrl = val;
if (sysinfo->dsize > 1)
- mmdc1->mpodtctrl = val;
+ MMDC1(mpodtctrl, val);
/* complete calibration */
val = (1 << 11); /* Force measurement on delay-lines */
mmdc0->mpmur0 = val;
if (sysinfo->dsize > 1)
- mmdc1->mpmur0 = val;
+ MMDC1(mpmur0, val);
/* Step 1: configuration request */
mmdc0->mdscr = (u32)(1 << 15); /* config request */
val = 0xa1390001; /* one-time HW ZQ calib */
mmdc0->mpzqhwctrl = val;
if (sysinfo->dsize > 1)
- mmdc1->mpzqhwctrl = val;
+ MMDC1(mpzqhwctrl, val);
/* Step 7: Enable MMDC with desired chip select */
mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
/* MR2 */
val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
((tcwl - 3) & 3) << 3;
+ debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
mmdc0->mdscr = MR(val, 2, 3, cs);
/* MR3 */
+ debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
mmdc0->mdscr = MR(0, 3, 3, cs);
/* MR1 */
val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
+ debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
mmdc0->mdscr = MR(val, 1, 3, cs);
/* MR0 */
val = ((tcl - 1) << 4) | /* CAS */
(1 << 8) | /* DLL Reset */
- ((twr - 3) << 9); /* Write Recovery */
+ ((twr - 3) << 9) | /* Write Recovery */
+ (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
+ debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
mmdc0->mdscr = MR(val, 0, 3, cs);
/* ZQ calibration */
val = (1 << 10);
mmdc0->mdpdc = (tcke & 0x7) << 16 |
5 << 12 | /* PWDT_1: 256 cycles */
5 << 8 | /* PWDT_0: 256 cycles */
- 1 << 7 | /* SLOW_PD */
1 << 6 | /* BOTH_CS_PD */
(tcksrx & 0x7) << 3 |
(tcksre & 0x7);
+ if (!sysinfo->pd_fast_exit)
+ mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
val = 0xa1390003;
mmdc0->mpzqhwctrl = val;
if (sysinfo->dsize > 1)
- mmdc1->mpzqhwctrl = val;
+ MMDC1(mpzqhwctrl, val);
/* Step 12: Configure and activate periodic refresh */
mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
projects / karo-tx-uboot.git / blobdiff