#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/regs-ocotp.h>
#include <asm/arch/clock.h>
+#include <asm/arch/dma.h>
#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#ifdef CONFIG_VIDEO_IPUV3
+#include <ipu.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TEMPERATURE_MIN -40
+#define TEMPERATURE_HOT 80
+#define TEMPERATURE_MAX 125
+#define REG_VALUE_TO_CEL(ratio, raw) ((raw_n40c - raw) * 100 / ratio - 40)
+
+#define __data __attribute__((section(".data")))
+
+struct scu_regs {
+ u32 ctrl;
+ u32 config;
+ u32 status;
+ u32 invalidate;
+ u32 fpga_rev;
+};
+
+#ifdef CONFIG_HW_WATCHDOG
+#define wdog_base ((void *)WDOG1_BASE_ADDR)
+#define WDOG_WCR 0x00
+#define WCR_WDE (1 << 2)
+#define WDOG_WSR 0x02
+
+void hw_watchdog_reset(void)
+{
+ if (readw(wdog_base + WDOG_WCR) & WCR_WDE) {
+ static u16 toggle = 0xaaaa;
+ static int first = 1;
+
+ if (first) {
+ printf("Watchdog active\n");
+ first = 0;
+ }
+ writew(toggle, wdog_base + WDOG_WSR);
+ toggle ^= 0xffff;
+ }
+}
+#endif
u32 get_cpu_rev(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int reg = readl(&anatop->digprog);
+ u32 reg = readl(&anatop->digprog_sololite);
+ u32 type = ((reg >> 16) & 0xff);
- /* Read mx6 variant: quad, dual or solo */
- int system_rev = (reg >> 4) & 0xFF000;
- /* Read mx6 silicon revision */
- system_rev |= (reg & 0xFF) + 0x10;
+ if (type != MXC_CPU_MX6SL) {
+ reg = readl(&anatop->digprog);
+ type = ((reg >> 16) & 0xff);
+ if (type == MXC_CPU_MX6DL) {
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ u32 cfg = readl(&scu->config) & 3;
- return system_rev;
+ if (!cfg)
+ type = MXC_CPU_MX6SOLO;
+ }
+ }
+ reg &= 0xff; /* mx6 silicon revision */
+ return (type << 12) | (reg + 0x10);
}
-#ifdef CONFIG_ARCH_CPU_INIT
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;
* Possible values are from 0.725V to 1.450V in steps of
* 0.025V (25mV).
*/
-void set_vddsoc(u32 mv)
+static void set_vddsoc(u32 mv)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
u32 val, reg = readl(&anatop->reg_core);
writel(reg, &anatop->reg_core);
}
+static u32 __data thermal_calib;
+
+int read_cpu_temperature(void)
+{
+ unsigned int reg, tmp, i;
+ unsigned int raw_25c, raw_hot, hot_temp, raw_n40c, ratio;
+ int temperature;
+ struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
+ struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
+
+ if (!thermal_calib) {
+ ocotp_clk_enable();
+ writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
+ thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
+ writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
+ ocotp_clk_disable();
+ }
+
+ if (thermal_calib == 0 || thermal_calib == 0xffffffff)
+ return TEMPERATURE_MIN;
+
+ /* Fuse data layout:
+ * [31:20] sensor value @ 25C
+ * [19:8] sensor value of hot
+ * [7:0] hot temperature value */
+ raw_25c = thermal_calib >> 20;
+ raw_hot = (thermal_calib & 0xfff00) >> 8;
+ hot_temp = thermal_calib & 0xff;
+
+ ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
+ raw_n40c = raw_25c + (13 * ratio) / 20;
+
+ /* now we only using single measure, every time we measure
+ the temperature, we will power on/down the anadig module*/
+ writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
+ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
+
+ /* write measure freq */
+ reg = readl(&anatop->tempsense1);
+ reg &= ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ;
+ reg |= 327;
+ writel(reg, &anatop->tempsense1);
+
+ writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
+ writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
+ writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
+
+ tmp = 0;
+ /* read five times of temperature values to get average*/
+ for (i = 0; i < 5; i++) {
+ while ((readl(&anatop->tempsense0) &
+ BM_ANADIG_TEMPSENSE0_FINISHED) == 0)
+ udelay(10000);
+ reg = readl(&anatop->tempsense0);
+ tmp += (reg & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >>
+ BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
+ writel(BM_ANADIG_TEMPSENSE0_FINISHED,
+ &anatop->tempsense0_clr);
+ }
+
+ tmp = tmp / 5;
+ if (tmp <= raw_n40c)
+ temperature = REG_VALUE_TO_CEL(ratio, tmp);
+ else
+ temperature = TEMPERATURE_MIN;
+
+ /* power down anatop thermal sensor */
+ writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
+ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
+
+ return temperature;
+}
+
+int check_cpu_temperature(int boot)
+{
+ static int __data max_temp;
+ int boot_limit = TEMPERATURE_HOT;
+ int tmp = read_cpu_temperature();
+
+debug("max_temp[%p]=%d diff=%d\n", &max_temp, max_temp, tmp - max_temp);
+
+ if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
+ printf("Temperature: can't get valid data!\n");
+ return tmp;
+ }
+
+ while (tmp >= boot_limit) {
+ if (boot) {
+ printf("CPU is %d C, too hot to boot, waiting...\n",
+ tmp);
+ udelay(5000000);
+ tmp = read_cpu_temperature();
+ boot_limit = TEMPERATURE_HOT - 1;
+ } else {
+ printf("CPU is %d C, too hot, resetting...\n",
+ tmp);
+ udelay(1000000);
+ reset_cpu(0);
+ }
+ }
+
+ if (boot) {
+ printf("Temperature: %d C, calibration data 0x%x\n",
+ tmp, thermal_calib);
+ } else if (tmp > max_temp) {
+ if (tmp > TEMPERATURE_HOT - 5)
+ printf("WARNING: CPU temperature %d C\n", tmp);
+ max_temp = tmp;
+ }
+ return tmp;
+}
+
int arch_cpu_init(void)
{
init_aips();
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
+#ifdef CONFIG_VIDEO_IPUV3
+ gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
+#endif
+#ifdef CONFIG_APBH_DMA
+ /* Timer is required for Initializing APBH DMA */
+ timer_init();
+ mxs_dma_init();
+#endif
return 0;
}
-#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
u32 value = readl(&fuse->mac_addr_high);
mac[0] = (value >> 8);
- mac[1] = value ;
+ mac[1] = value;
value = readl(&fuse->mac_addr_low);
- mac[2] = value >> 24 ;
- mac[3] = value >> 16 ;
- mac[4] = value >> 8 ;
- mac[5] = value ;
-
+ mac[2] = value >> 24;
+ mac[3] = value >> 16;
+ mac[4] = value >> 8;
+ mac[5] = value;
}
#endif
+
+void boot_mode_apply(unsigned cfg_val)
+{
+ unsigned reg;
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ writel(cfg_val, &psrc->gpr9);
+ reg = readl(&psrc->gpr10);
+ if (cfg_val)
+ reg |= 1 << 28;
+ else
+ reg &= ~(1 << 28);
+ writel(reg, &psrc->gpr10);
+}
+/*
+ * cfg_val will be used for
+ * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
+ * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
+ * to SBMR1, which will determine the boot device.
+ */
+const struct boot_mode soc_boot_modes[] = {
+ {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
+ /* reserved value should start rom usb */
+ {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
+ {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
+ {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
+ {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
+ {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
+ {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
+ /* 4 bit bus width */
+ {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+ {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#define RESET_MAX_TIMEOUT 1000000
+#define MXS_BLOCK_SFTRST (1 << 31)
+#define MXS_BLOCK_CLKGATE (1 << 30)
+#include <div64.h>
+
+static const int scale = 1;
+
+int mxs_wait_mask_set(struct mx6_register_32 *mx6_reg, uint32_t mask, unsigned long timeout)
+{
+ unsigned long loops = 0;
+
+ timeout /= scale;
+ if (timeout == 0)
+ timeout++;
+
+ /* Wait for at least one microsecond for the bit mask to be set */
+ while ((readl(&mx6_reg->reg) & mask) != mask) {
+ if ((loops += scale) >= timeout) {
+ printf("MASK %08x in %p not set after %lu ticks\n",
+ mask, &mx6_reg->reg, loops * scale);
+ return 1;
+ }
+ udelay(scale);
+ }
+ if (loops == 0)
+ udelay(1);
+
+ return 0;
+}
+
+int mxs_wait_mask_clr(struct mx6_register_32 *mx6_reg, uint32_t mask, unsigned long timeout)
+{
+ unsigned long loops = 0;
+
+ timeout /= scale;
+ if (timeout == 0)
+ timeout++;
+
+ /* Wait for at least one microsecond for the bit mask to be cleared */
+ while ((readl(&mx6_reg->reg) & mask) != 0) {
+ if ((loops += scale) >= timeout) {
+ printf("MASK %08x in %p not cleared after %lu ticks\n",
+ mask, &mx6_reg->reg, loops * scale);
+ return 1;
+ }
+ udelay(scale);
+ }
+ if (loops == 0)
+ udelay(1);
+
+ return 0;
+}
+
+int mxs_reset_block(struct mx6_register_32 *mx6_reg)
+{
+ /* Clear SFTRST */
+ writel(MXS_BLOCK_SFTRST, &mx6_reg->reg_clr);
+
+ if (mxs_wait_mask_clr(mx6_reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) {
+ printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n",
+ &mx6_reg->reg, readl(&mx6_reg->reg));
+ return 1;
+ }
+
+ /* Clear CLKGATE */
+ writel(MXS_BLOCK_CLKGATE, &mx6_reg->reg_clr);
+
+ /* Set SFTRST */
+ writel(MXS_BLOCK_SFTRST, &mx6_reg->reg_set);
+
+ /* Wait for CLKGATE being set */
+ if (mxs_wait_mask_set(mx6_reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) {
+ printf("TIMEOUT waiting for CLKGATE[%p] to set: %08x\n",
+ &mx6_reg->reg, readl(&mx6_reg->reg));
+ return 0;
+ }
+
+ /* Clear SFTRST */
+ writel(MXS_BLOCK_SFTRST, &mx6_reg->reg_clr);
+
+ if (mxs_wait_mask_clr(mx6_reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) {
+ printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n",
+ &mx6_reg->reg, readl(&mx6_reg->reg));
+ return 1;
+ }
+
+ /* Clear CLKGATE */
+ writel(MXS_BLOCK_CLKGATE, &mx6_reg->reg_clr);
+
+ if (mxs_wait_mask_clr(mx6_reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) {
+ printf("TIMEOUT waiting for CLKGATE[%p] to clear: %08x\n",
+ &mx6_reg->reg, readl(&mx6_reg->reg));
+ return 1;
+ }
+
+ return 0;
+}
projects / karo-tx-uboot.git / blobdiff