*/
#include <common.h>
-#include <stdbool.h>
-#include <dm.h>
#include <div64.h>
#include <ipu.h>
-#include <imx_thermal.h>
#include <asm/armv7.h>
#include <asm/bootm.h>
#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/regs-ocotp.h>
#include <asm/arch/clock.h>
-#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/regs-ocotp.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
+#include <stdbool.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <dm.h>
+#include <imx_thermal.h>
DECLARE_GLOBAL_DATA_PTR;
struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
if (!thermal_calib) {
- ocotp_clk_enable();
+ enable_ocotp_clk(1);
writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
- ocotp_clk_disable();
+ enable_ocotp_clk(0);
}
if (thermal_calib == 0 || thermal_calib == 0xffffffff)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
-
-#ifdef CONFIG_MX6SX
struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
- writew(enable, &wdog3->wmcr);
-#endif
+
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+ writew(enable, &wdog3->wmcr);
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
u32 mask528;
u32 reg, periph1, periph2;
- if (is_cpu_type(MXC_CPU_MX6SX))
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs