am33xx/omap: Allow cache enable for all Sitara/OMAP

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap-common / hwinit-common.c

diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index ba97d9ec565af9ea4d83e1c69118868ffed43063..5f50a1980157d646b1308bf8d98b529009d40d1e 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -18,13 +18,8 @@
 #include <asm/emif.h>
 #include <asm/omap_common.h>
 #include <linux/compiler.h>
-#include <asm/cache.h>
 #include <asm/system.h>
 
-#define ARMV7_DCACHE_WRITEBACK  0xe
-#define        ARMV7_DOMAIN_CLIENT     1
-#define ARMV7_DOMAIN_MASK      (0x3 << 0)
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
@@ -263,40 +258,3 @@ int print_cpuinfo(void)
        return 0;
 }
 #endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-       /* Enable D-cache. I-cache is already enabled in start.S */
-       dcache_enable();
-}
-
-void dram_bank_mmu_setup(int bank)
-{
-       bd_t *bd = gd->bd;
-       int     i;
-
-       u32 start = bd->bi_dram[bank].start >> 20;
-       u32 size = bd->bi_dram[bank].size >> 20;
-       u32 end = start + size;
-
-       debug("%s: bank: %d\n", __func__, bank);
-       for (i = start; i < end; i++)
-               set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
-
-}
-
-void arm_init_domains(void)
-{
-       u32 reg;
-
-       reg = get_dacr();
-       /*
-       * Set DOMAIN to client access so that all permissions
-       * set in pagetables are validated by the mmu.
-       */
-       reg &= ~ARMV7_DOMAIN_MASK;
-       reg |= ARMV7_DOMAIN_CLIENT;
-       set_dacr(reg);
-}
-#endif