Add GPL-2.0+ SPDX-License-Identifier to source files

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap3 / clock.c

diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 567817e0ec3b062c3ee2a66c901b14ab1b44a8b2..3acbc9c864cf379e9a69a102fcc9b1a69b3c2dc6 100644 (file)
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -9,25 +9,12 @@
  *      Richard Woodruff <r-woodruff2@ti.com>
  *      Syed Mohammed Khasim <khasim@ti.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/clocks_omap3.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/sys_proto.h>
@@ -572,6 +559,22 @@ void prcm_init(void)
        }
 
        if (get_cpu_family() == CPU_OMAP36XX) {
+               /*
+                * In warm reset conditions on OMAP36xx/AM/DM37xx
+                * the rom code incorrectly sets the DPLL4 clock
+                * input divider to /6.5. Section 3.5.3.3.3.2.1 of
+                * the AM/DM37x TRM explains that the /6.5 divider
+                * is used only when the input clock is 13MHz.
+                *
+                * If the part is in this cpu family *and* the input
+                * clock *is not* 13 MHz, then reset the DPLL4 clock
+                * input divider to /1 as it should never set to /6.5
+                * in this case.
+                */
+               if (sys_clkin_sel != 1) /* 13 MHz */
+                       /* Bit 8: DPLL4_CLKINP_DIV */
+                       sr32(&prm_base->clksrc_ctrl, 8, 1, 0);
+
                /* Unlock MPU DPLL (slows things down, and needed later) */
                sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
                wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,