void do_io_settings(void)
{
u32 io_settings = 0, mask = 0;
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
/* Impedance settings EMMC, C2C 1,2, hsi2 */
mask = (ds_mask << 2) | (ds_mask << 8) |
(sc_fast << 17) | (sc_fast << 14);
writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
- if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+ if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
io_settings_lpddr2();
else
io_settings_ddr3();
{
omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
}
+
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev)
+{
+
+#ifdef CONFIG_ARM_ERRATA_801819
+ /*
+ * DRA72x processors are uniprocessors and DONOT have
+ * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
+ * Extensions) Hence the erratum workaround is not applicable for
+ * DRA72x processors.
+ */
+ if (is_dra72x())
+ acr &= ~((0x3 << 23) | (0x3 << 25));
+#endif
+ omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
+}