* Aneesh V <aneesh@ti.com>
* Sricharan R <r.sricharan@ti.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/emif.h>
.emif_ddr_ext_phy_ctrl_5 = 0x04010040
};
+const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
+ .sdram_config_init = 0x80800EBA,
+ .sdram_config = 0x808022BA,
+ .ref_ctrl = 0x0000081A,
+ .sdram_tim1 = 0x772F6873,
+ .sdram_tim2 = 0x304a129a,
+ .sdram_tim3 = 0x02f7e45f,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x100b3215,
+ .temp_alert_config = 0x08000a05,
+ .emif_ddr_phy_ctlr_1_init = 0x0E30400d,
+ .emif_ddr_phy_ctlr_1 = 0x0E30400d,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
+ .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
+ .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
+ .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
+};
+
const struct emif_regs emif_regs_266_mhz_2cs = {
.sdram_config_init = 0x80800EBA,
.sdram_config = 0x808022BA,
const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
+ .sdram_config2 = 0x0,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.emif_rd_wr_exec_thresh = 0x00000305
};
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
+ .sdram_config_init = 0x61851B32,
+ .sdram_config = 0x61851B32,
+ .sdram_config2 = 0x0,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xCCCF36B3,
+ .sdram_tim2 = 0x308F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x1007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0030400A,
+ .emif_ddr_phy_ctlr_1 = 0x0034400A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x40000305
+};
+
+const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
+ .sdram_config_init = 0x61851ab2,
+ .sdram_config = 0x61851ab2,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xCCCF36B3,
+ .sdram_tim2 = 0x308F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x0007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0E20400A,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x009E009E,
+ .emif_ddr_ext_phy_ctrl_3 = 0x009E009E,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009E009E,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
+ .sdram_config_init = 0x61851B32,
+ .sdram_config = 0x61851B32,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xCCCF36B3,
+ .sdram_tim2 = 0x308F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x0007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0020400A,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x009D009D,
+ .emif_ddr_ext_phy_ctrl_3 = 0x009D009D,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009D009D,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009D009D,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80740300,
- .dmm_lisa_map_3 = 0xFF020100
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
+/*
+ * DRA752 EVM board has 1.5 GB of memory
+ * EMIF1 --> 2Gb * 2 = 512MB
+ * EMIF2 --> 2Gb * 4 = 1GB
+ * so mapping 1GB interleaved and 512MB non-interleaved
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x80640300,
+ .dmm_lisa_map_2 = 0xC0500220,
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
+/*
+ * DRA752 EVM EMIF1 ONLY CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x0,
+ .dmm_lisa_map_2 = 0x80500100,
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
+/*
+ * DRA752 EVM EMIF2 ONLY CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x0,
+ .dmm_lisa_map_2 = 0x80600200,
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
case OMAP5432_ES1_0:
*regs = &emif_regs_ddr3_532_mhz_1cs;
break;
+ case OMAP5430_ES2_0:
+ *regs = &emif_regs_532_mhz_2cs_es2;
+ break;
+ case OMAP5432_ES2_0:
+ *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
+ break;
+ case DRA752_ES1_0:
+ switch (emif_nr) {
+ case 1:
+ *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
+ break;
+ case 2:
+ *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
+ break;
+ }
+ break;
default:
- *regs = &emif_regs_ddr3_532_mhz_1cs;
+ *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
}
}
static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
**dmm_lisa_regs)
{
- *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
+ switch (omap_revision()) {
+ case OMAP5430_ES1_0:
+ case OMAP5430_ES2_0:
+ case OMAP5432_ES1_0:
+ case OMAP5432_ES2_0:
+ *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
+ break;
+ case DRA752_ES1_0:
+ default:
+ *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
+ }
+
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
0x00000000,
0x00000000,
0x00000000,
- 0x00000077
+ 0x00000077,
+ 0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00000000,
0x00000000,
0x00000000,
- 0x00000057
+ 0x00000057,
+ 0x0
+};
+
+const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x50D4350D,
+ 0x00000D43,
+ 0x04010040,
+ 0x01004010,
+ 0x00001004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x80080080,
+ 0x00800800,
+ 0x08102040,
+ 0x00000002,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000057,
+ 0x0
+};
+
+const u32
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x009E009E,
+ 0x002E002E,
+ 0x002E002E,
+ 0x002E002E,
+ 0x002E002E,
+ 0x002E002E,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x0,
+ 0x600020,
+ 0x40010080,
+ 0x8102040
+};
+
+const u32
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x009D009D,
+ 0x002D002D,
+ 0x002D002D,
+ 0x002D002D,
+ 0x002D002D,
+ 0x002D002D,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x0,
+ 0x600020,
+ 0x40010080,
+ 0x8102040
};
const struct lpddr2_mr_regs mr_regs = {
.mr16 = MR16_REF_FULL_ARRAY
};
-static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
+static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs)
{
switch (omap_revision()) {
case OMAP5430_ES1_0:
+ case OMAP5430_ES2_0:
*regs = ext_phy_ctrl_const_base;
break;
case OMAP5432_ES1_0:
*regs = ddr3_ext_phy_ctrl_const_base_es1;
break;
+ case OMAP5432_ES2_0:
+ *regs = ddr3_ext_phy_ctrl_const_base_es2;
+ break;
+ case DRA752_ES1_0:
+ if (emif_nr == 1)
+ *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
+ else
+ *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
+ break;
default:
- *regs = ddr3_ext_phy_ctrl_const_base_es1;
+ *regs = ddr3_ext_phy_ctrl_const_base_es2;
+
}
}
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
+ u32 emif_nr;
const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
+ emif_nr = (base == EMIF1_BASE) ? 1 : 2;
+
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
* external phy 6-24 registers do not change with
* ddr frequency
*/
- emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
+ emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs);
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
writel(ext_phy_ctrl_const_regs[i],
emif_ext_phy_ctrl_base++);
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