#include <asm/arch/hardware.h>
/* AM335X EMIF Register values */
-#define EMIF_SDMGT 0x80000000
-#define EMIF_SDRAM 0x00004650
-#define EMIF_PHYCFG 0x2
#define DDR_PHY_RESET (0x1 << 10)
#define DDR_FUNCTIONAL_MODE_EN 0x1
#define DDR_PHY_READY (0x1 << 2)
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
#define VTP_CTRL_LOCK_EN (0x1 << 4)
-#define VTP_CTRL_START_EN (0x1)
-#define DDR2_RATIO 0x80
-#define CMD_FORCE 0x00
-#define CMD_DELAY 0x00
-
-#define EMIF_READ_LATENCY 0x05
-#define EMIF_TIM1 0x0666B3D6
-#define EMIF_TIM2 0x143731DA
-#define EMIF_TIM3 0x00000347
-#define EMIF_SDCFG 0x43805332
-#define EMIF_SDREF 0x0000081a
-#define DDR2_DLL_LOCK_DIFF 0x0
-#define DDR2_RD_DQS 0x12
-#define DDR2_PHY_FIFO_WE 0x80
-
-#define DDR2_INVERT_CLKOUT 0x00
-#define DDR2_WR_DQS 0x00
-#define DDR2_PHY_WRLVL 0x00
-#define DDR2_PHY_GATELVL 0x00
-#define DDR2_PHY_WR_DATA 0x40
-#define PHY_RANK0_DELAY 0x01
-#define PHY_DLL_LOCK_DIFF 0x0
-#define DDR_IOCTRL_VALUE 0x18B
+#define VTP_CTRL_START_EN (0x1 << 0)
/**
* This structure represents the EMIF registers on AM33XX devices.
/**
* This structure represents the DDR registers on AM33XX devices.
*/
+/* data macro cells */
+struct ddr_dt_regs {
+ unsigned int rdsratio0; /* offset 0x0C8 */
+ unsigned int rdsratio1; /* offset 0x0CC */
+ unsigned int resv4[3];
+ unsigned int wdsratio0; /* offset 0x0DC */
+ unsigned int wdsratio1; /* offset 0x0E0 */
+ unsigned int resv5[3];
+ unsigned int wiratio0; /* offset 0x0F0 */
+ unsigned int wiratio1; /* offset 0x0F4 */
+ unsigned int wimode0; /* offset 0x0F8 */
+ unsigned int giratio0; /* offset 0x0FC */
+ unsigned int giratio1; /* offset 0x100 */
+ unsigned int gimode0; /* offset 0x104 */
+ unsigned int fwsratio0; /* offset 0x108 */
+ unsigned int fwsratio1; /* offset 0x10C */
+ unsigned int resv7[4];
+ unsigned int wrsratio0; /* offset 0x120 */
+ unsigned int wrsratio1; /* offset 0x124 */
+ unsigned int resv8[3];
+ unsigned int rdelays0; /* offset 0x134 */
+ unsigned int dldiff0; /* offset 0x138 */
+ unsigned int resv9[12];
+};
+
struct ddr_regs {
unsigned int resv0[7];
unsigned int cm0csratio; /* offset 0x01C */
unsigned int cm2dldiff; /* offset 0x090 */
unsigned int cm2iclkout; /* offset 0x094 */
unsigned int resv3[12];
- unsigned int dt0rdsratio0; /* offset 0x0C8 */
- unsigned int dt0rdsratio1; /* offset 0x0CC */
- unsigned int resv4[3];
- unsigned int dt0wdsratio0; /* offset 0x0DC */
- unsigned int dt0wdsratio1; /* offset 0x0E0 */
- unsigned int resv5[3];
- unsigned int dt0wiratio0; /* offset 0x0F0 */
- unsigned int dt0wiratio1; /* offset 0x0F4 */
- unsigned int dt0giratio0; /* offset 0x0FC */
- unsigned int dt0giratio1; /* offset 0x100 */
- unsigned int resv6[1];
- unsigned int dt0fwsratio0; /* offset 0x108 */
- unsigned int dt0fwsratio1; /* offset 0x10C */
- unsigned int resv7[4];
- unsigned int dt0wrsratio0; /* offset 0x120 */
- unsigned int dt0wrsratio1; /* offset 0x124 */
- unsigned int resv8[3];
- unsigned int dt0rdelays0; /* offset 0x134 */
- unsigned int dt0dldiff0; /* offset 0x138 */
- unsigned int resv9[39];
- unsigned int dt1rdelays0; /* offset 0x1D8 */
+ struct ddr_dt_regs dt0;
+ struct ddr_dt_regs dt1;
};
/**