nand: lpc32xx: add SLC NAND controller support

[karo-tx-uboot.git] / arch / arm / include / asm / arch-lpc32xx / clk.h

diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
index c1dad0a44453b5dd097b050f5dd828a08cf29d90..010211a7e102b0ef1b3a72304147007952ec5684 100644 (file)
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -1,20 +1,7 @@
 /*
  * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _LPC32XX_CLK_H
@@ -84,6 +71,7 @@ struct clk_pm_regs {
 };
 
 /* HCLK Divider Control Register bits */
+#define CLK_HCLK_DDRAM_MASK            (0x3 << 7)
 #define CLK_HCLK_DDRAM_HALF            (0x2 << 7)
 #define CLK_HCLK_DDRAM_NOMINAL         (0x1 << 7)
 #define CLK_HCLK_DDRAM_STOPPED         (0x0 << 7)
@@ -136,6 +124,10 @@ struct clk_pm_regs {
 #define CLK_MAC_SLAVE                  (1 << 1)
 #define CLK_MAC_REG                    (1 << 0)
 
+/* I2C Clock Control Register bits     */
+#define CLK_I2C2_ENABLE                        (1 << 1)
+#define CLK_I2C1_ENABLE                        (1 << 0)
+
 /* Timer Clock Control1 Register bits */
 #define CLK_TIMCLK_MOTOR               (1 << 6)
 #define CLK_TIMCLK_TIMER3              (1 << 5)
@@ -160,11 +152,24 @@ struct clk_pm_regs {
 /* DMA Clock Control Register bits */
 #define CLK_DMA_ENABLE                 (1 << 0)
 
+/* NAND Clock Control Register bits */
+#define CLK_NAND_SLC                   (1 << 0)
+#define CLK_NAND_MLC                   (1 << 1)
+#define CLK_NAND_SLC_SELECT            (1 << 2)
+#define CLK_NAND_MLC_INT               (1 << 5)
+
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK          (1 << 0)
+
+/* SDRAMCLK register bits */
+#define CLK_SDRAM_DDR_SEL              (1 << 1)
+
 unsigned int get_sys_clk_rate(void);
 unsigned int get_hclk_pll_rate(void);
 unsigned int get_hclk_clk_div(void);
 unsigned int get_hclk_clk_rate(void);
 unsigned int get_periph_clk_div(void);
 unsigned int get_periph_clk_rate(void);
+unsigned int get_sdram_clk_rate(void);
 
 #endif /* _LPC32XX_CLK_H */