Merge branch 'master' of git://git.denx.de/u-boot-nios

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx31 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 552c8214e47ee7c0b9df3e1416a14c0b6630ff64..0147920e4b3797293fd6652b5a027e52e72b472a 100644 (file)
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -98,6 +98,12 @@ struct iim_regs {
        u32 iim_scs3;
 };
 
+struct iomuxc_regs {
+       u32 unused1;
+       u32 unused2;
+       u32 gpr;
+};
+
 struct mx3_cpu_type {
        u8 srev;
        u32 v;
@@ -468,6 +474,44 @@ enum iomux_pins {
        MX31_PIN_CAPTURE        = IOMUX_PIN(7,    327),
 };
 
+/*
+ * various IOMUX general purpose functions
+ */
+enum iomux_gp_func {
+       MUX_PGP_FIRI                    = 1 << 0,
+       MUX_DDR_MODE                    = 1 << 1,
+       MUX_PGP_CSPI_BB                 = 1 << 2,
+       MUX_PGP_ATA_1                   = 1 << 3,
+       MUX_PGP_ATA_2                   = 1 << 4,
+       MUX_PGP_ATA_3                   = 1 << 5,
+       MUX_PGP_ATA_4                   = 1 << 6,
+       MUX_PGP_ATA_5                   = 1 << 7,
+       MUX_PGP_ATA_6                   = 1 << 8,
+       MUX_PGP_ATA_7                   = 1 << 9,
+       MUX_PGP_ATA_8                   = 1 << 10,
+       MUX_PGP_UH2                     = 1 << 11,
+       MUX_SDCTL_CSD0_SEL              = 1 << 12,
+       MUX_SDCTL_CSD1_SEL              = 1 << 13,
+       MUX_CSPI1_UART3                 = 1 << 14,
+       MUX_EXTDMAREQ2_MBX_SEL          = 1 << 15,
+       MUX_TAMPER_DETECT_EN            = 1 << 16,
+       MUX_PGP_USB_4WIRE               = 1 << 17,
+       MUX_PGP_USB_COMMON              = 1 << 18,
+       MUX_SDHC_MEMSTICK1              = 1 << 19,
+       MUX_SDHC_MEMSTICK2              = 1 << 20,
+       MUX_PGP_SPLL_BYP                = 1 << 21,
+       MUX_PGP_UPLL_BYP                = 1 << 22,
+       MUX_PGP_MSHC1_CLK_SEL           = 1 << 23,
+       MUX_PGP_MSHC2_CLK_SEL           = 1 << 24,
+       MUX_CSPI3_UART5_SEL             = 1 << 25,
+       MUX_PGP_ATA_9                   = 1 << 26,
+       MUX_PGP_USB_SUSPEND             = 1 << 27,
+       MUX_PGP_USB_OTG_LOOPBACK        = 1 << 28,
+       MUX_PGP_USB_HS1_LOOPBACK        = 1 << 29,
+       MUX_PGP_USB_HS2_LOOPBACK        = 1 << 30,
+       MUX_CLKO_DDR_MODE               = 1 << 31,
+};
+
 /* Bit definitions for RCSR register in CCM */
 #define CCM_RCSR_NF16B (1 << 31)
 #define CCM_RCSR_NFMS  (1 << 30)
@@ -484,6 +528,17 @@ struct mx31_weim {
        struct mx31_weim_cscr cscr[6];
 };
 
+/* ESD control registers */
+struct esdc_regs {
+       u32 ctl0;
+       u32 cfg0;
+       u32 ctl1;
+       u32 cfg1;
+       u32 misc;
+       u32 dly[5];
+       u32 dlyl;
+};
+
 #endif
 
 #define __REG(x)     (*((volatile u32 *)(x)))
@@ -562,6 +617,8 @@ struct mx31_weim {
 #define ESDCTL_BL(x)                   ((x) << 7)
 #define ESDCTL_PRCT(x)                 ((x) << 0)
 
+#define ESDCTL_BASE_ADDR       0xB8001000
+
 /* 13 fields of the upper CS control register */
 #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
                cnc, wsc, ew, wws, edc) \
@@ -585,7 +642,6 @@ struct mx31_weim {
 #define WEIM_BASE      0xb8002000
 
 #define IOMUXC_BASE    0x43FAC000
-#define IOMUXC_GPR     (IOMUXC_BASE + 0x8)
 #define IOMUXC_SW_MUX_CTL(x)   (IOMUXC_BASE + 0xc + (x) * 4)
 #define IOMUXC_SW_PAD_CTL(x)   (IOMUXC_BASE + 0x154 + (x) * 4)
 
@@ -642,12 +698,23 @@ struct mx31_weim {
 
 /* Register offsets based on IOMUXC_BASE */
 /* 0x00 .. 0x7b */
+#define MUX_CTL_CSPI3_MISO             0x0c
+#define MUX_CTL_CSPI3_SCLK             0x0d
+#define MUX_CTL_CSPI3_SPI_RDY  0x0e
+#define MUX_CTL_CSPI3_MOSI             0x13
+
 #define MUX_CTL_USBH2_DATA1    0x40
 #define MUX_CTL_USBH2_DIR      0x44
 #define MUX_CTL_USBH2_STP      0x45
 #define MUX_CTL_USBH2_NXT      0x46
 #define MUX_CTL_USBH2_DATA0    0x47
 #define MUX_CTL_USBH2_CLK      0x4B
+
+#define MUX_CTL_TXD2           0x70
+#define MUX_CTL_RTS2           0x71
+#define MUX_CTL_CTS2           0x72
+#define MUX_CTL_RXD2           0x77
+
 #define MUX_CTL_RTS1           0x7c
 #define MUX_CTL_CTS1           0x7d
 #define MUX_CTL_DTR_DCE1       0x7e
@@ -705,6 +772,11 @@ struct mx31_weim {
 #define MUX_RTS1__UART1_RTS_B  IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
 #define MUX_CTS1__UART1_CTS_B  IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
 
+#define MUX_RXD2__UART2_RXD_MUX        IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
+#define MUX_TXD2__UART2_TXD_MUX        IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
+#define MUX_RTS2__UART2_RTS_B  IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
+#define MUX_CTS2__UART2_CTS_B  IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
+
 #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
 #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
 #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)