Unified codebase for TX28, TX48, TX51, TX53

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx5 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 4fa66587a0b7dabdd9a76ba0dd7aaf02a47d5882..6f06c88568d995c7619aadb6d15182f7cda0c5a6 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -26,23 +26,24 @@
 #if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR         0x1FFE0000      /* internal ram */
 #define IPU_CTRL_BASE_ADDR     0x40000000
-#define SPBA0_BASE_ADDR         0x70000000
-#define AIPS1_BASE_ADDR         0x73F00000
-#define AIPS2_BASE_ADDR         0x83F00000
-#define CSD0_BASE_ADDR          0x90000000
-#define CSD1_BASE_ADDR          0xA0000000
-#define NFC_BASE_ADDR_AXI       0xCFFF0000
-#define CS1_BASE_ADDR           0xB8000000
+#define SPBA0_BASE_ADDR                0x70000000
+#define AIPS1_BASE_ADDR                0x73F00000
+#define AIPS2_BASE_ADDR                0x83F00000
+#define CSD0_BASE_ADDR         0x90000000
+#define CSD1_BASE_ADDR         0xA0000000
+#define NFC_BASE_ADDR_AXI      0xCFFF0000
+#define CS1_BASE_ADDR          0xB8000000
 #elif defined(CONFIG_MX53)
-#define IPU_CTRL_BASE_ADDR      0x18000000
-#define SPBA0_BASE_ADDR         0x50000000
-#define AIPS1_BASE_ADDR         0x53F00000
-#define AIPS2_BASE_ADDR         0x63F00000
-#define CSD0_BASE_ADDR          0x70000000
-#define CSD1_BASE_ADDR          0xB0000000
-#define NFC_BASE_ADDR_AXI       0xF7FF0000
-#define IRAM_BASE_ADDR          0xF8000000
-#define CS1_BASE_ADDR           0xF4000000
+#define IPU_CTRL_BASE_ADDR     0x00000000
+#define SPBA0_BASE_ADDR                0x50000000
+#define AIPS1_BASE_ADDR                0x53F00000
+#define AIPS2_BASE_ADDR                0x63F00000
+#define CSD0_BASE_ADDR         0x70000000
+#define CSD1_BASE_ADDR         0xB0000000
+#define NFC_BASE_ADDR_AXI      0xF7FF0000
+#define IRAM_BASE_ADDR         0xF8000000
+#define CS1_BASE_ADDR          0xF4000000
+#define SATA_BASE_ADDR         0x10000000
 #else
 #error "CPU_TYPE not defined"
 #endif
@@ -55,7 +56,7 @@
 #define MMC_SDHC1_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00004000)
 #define MMC_SDHC2_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00008000)
 #define UART3_BASE             (SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR        (SPBA0_BASE_ADDR + 0x00010000)
+#define CSPI1_BASE_ADDR                (SPBA0_BASE_ADDR + 0x00010000)
 #define SSI2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00014000)
 #define MMC_SDHC3_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00020000)
 #define MMC_SDHC4_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00024000)
@@ -90,9 +91,10 @@
 #define GPC_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000D8000)
 
 #if defined(CONFIG_MX53)
-#define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
-#define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
-#define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
+#define GPIO5_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000DC000)
+#define GPIO6_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000E0000)
+#define GPIO7_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000E4000)
+#define UART4_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000F0000)
 #endif
 /*
  * AIPS 2
@@ -107,7 +109,7 @@
 #define IIM_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00098000)
 #define CSU_BASE_ADDR          (AIPS2_BASE_ADDR + 0x0009C000)
 #define ARM_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000A4000)
+#define OWIRE_BASE_ADDR                (AIPS2_BASE_ADDR + 0x000A4000)
 #define FIRI_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000A8000)
 #define CSPI2_BASE_ADDR                (AIPS2_BASE_ADDR + 0x000AC000)
 #define SDMA_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000B0000)
@@ -133,6 +135,10 @@
 #define VPU_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000F4000)
 #define SAHARA_BASE_ADDR       (AIPS2_BASE_ADDR + 0x000F8000)
 
+#if defined(CONFIG_MX53)
+#define UART5_BASE_ADDR                (AIPS2_BASE_ADDR + 0x00090000)
+#endif
+
 /*
  * WEIM CSnGCR1
  */
@@ -255,7 +261,7 @@
 /*
  * Number of GPIO pins per port
  */
-#define GPIO_NUM_PIN            32
+#define GPIO_NUM_PIN   32
 
 #define IIM_SREV       0x24
 #define ROM_SI_REV     0x48
@@ -289,6 +295,10 @@
 #define DP_MFD_665     (96 - 1)
 #define DP_MFN_665     89
 
+#define DP_OP_600       ((6 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_600      (4 - 1)
+#define DP_MFN_600      1
+
 #define DP_OP_532      ((5 << 4) + ((1 - 1)  << 0))
 #define DP_MFD_532     (24 - 1)
 #define DP_MFN_532     13
@@ -297,20 +307,24 @@
 #define DP_MFD_400     (3 - 1)
 #define DP_MFN_400     1
 
+#define DP_OP_333      ((6 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_333     (16 - 1)
+#define DP_MFN_333     15
+
 #define DP_OP_216      ((6 << 4) + ((3 - 1)  << 0))
 #define DP_MFD_216     (4 - 1)
 #define DP_MFN_216     3
 
-#define CHIP_REV_1_0            0x10
-#define CHIP_REV_1_1            0x11
-#define CHIP_REV_2_0            0x20
-#define CHIP_REV_2_5           0x25
-#define CHIP_REV_3_0            0x30
+#define CHIP_REV_1_0   0x10
+#define CHIP_REV_1_1   0x11
+#define CHIP_REV_2_0   0x20
+#define CHIP_REV_2_5   0x25
+#define CHIP_REV_3_0   0x30
 
-#define BOARD_REV_1_0           0x0
-#define BOARD_REV_2_0           0x1
+#define BOARD_REV_1_0  0x0
+#define BOARD_REV_2_0  0x1
 
-#define IMX_IIM_BASE            (IIM_BASE_ADDR)
+#define IMX_IIM_BASE   IIM_BASE_ADDR
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
@@ -465,7 +479,7 @@ struct cspi_regs {
 struct iim_regs {
        u32     stat;
        u32     statm;
-       u32     err;
+       u32     err;
        u32     emask;
        u32     fctl;
        u32     ua;
@@ -485,12 +499,19 @@ struct iim_regs {
        } bank[4];
 };
 
+struct fuse_bank0_regs {
+       u32     fuse0_23[24];
+       u32     gp[8];
+};
+
 struct fuse_bank1_regs {
        u32     fuse0_8[9];
        u32     mac_addr[6];
        u32     fuse15_31[0x11];
 };
 
+extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
 #endif /* __ASSEMBLER__*/
 
 #endif                         /* __ASM_ARCH_MX5_IMX_REGS_H__ */