TX6 Release 2013-04-22

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx5 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 6f06c88568d995c7619aadb6d15182f7cda0c5a6..75d89b056cc75671501ad63e29b5086431b60750 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -23,26 +23,28 @@
 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
 #define __ASM_ARCH_MX5_IMX_REGS_H__
 
+#define ARCH_MXC
+
 #if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR         0x1FFE0000      /* internal ram */
 #define IPU_CTRL_BASE_ADDR     0x40000000
-#define SPBA0_BASE_ADDR                0x70000000
-#define AIPS1_BASE_ADDR                0x73F00000
-#define AIPS2_BASE_ADDR                0x83F00000
-#define CSD0_BASE_ADDR         0x90000000
-#define CSD1_BASE_ADDR         0xA0000000
-#define NFC_BASE_ADDR_AXI      0xCFFF0000
-#define CS1_BASE_ADDR          0xB8000000
+#define SPBA0_BASE_ADDR         0x70000000
+#define AIPS1_BASE_ADDR         0x73F00000
+#define AIPS2_BASE_ADDR         0x83F00000
+#define CSD0_BASE_ADDR          0x90000000
+#define CSD1_BASE_ADDR          0xA0000000
+#define NFC_BASE_ADDR_AXI       0xCFFF0000
+#define CS1_BASE_ADDR           0xB8000000
 #elif defined(CONFIG_MX53)
 #define IPU_CTRL_BASE_ADDR     0x00000000
-#define SPBA0_BASE_ADDR                0x50000000
-#define AIPS1_BASE_ADDR                0x53F00000
-#define AIPS2_BASE_ADDR                0x63F00000
-#define CSD0_BASE_ADDR         0x70000000
-#define CSD1_BASE_ADDR         0xB0000000
-#define NFC_BASE_ADDR_AXI      0xF7FF0000
-#define IRAM_BASE_ADDR         0xF8000000
-#define CS1_BASE_ADDR          0xF4000000
+#define SPBA0_BASE_ADDR         0x50000000
+#define AIPS1_BASE_ADDR         0x53F00000
+#define AIPS2_BASE_ADDR         0x63F00000
+#define CSD0_BASE_ADDR          0x70000000
+#define CSD1_BASE_ADDR          0xB0000000
+#define NFC_BASE_ADDR_AXI       0xF7FF0000
+#define IRAM_BASE_ADDR          0xF8000000
+#define CS1_BASE_ADDR           0xF4000000
 #define SATA_BASE_ADDR         0x10000000
 #else
 #error "CPU_TYPE not defined"
@@ -95,6 +97,7 @@
 #define GPIO6_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000E0000)
 #define GPIO7_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000E4000)
 #define UART4_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000F0000)
+#define I2C3_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000EC000)
 #endif
 /*
  * AIPS 2
@@ -303,6 +306,10 @@
 #define DP_MFD_532     (24 - 1)
 #define DP_MFN_532     13
 
+#define DP_OP_455      ((9 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_455     (48 - 1)
+#define DP_MFN_455     23
+
 #define DP_OP_400      ((8 << 4) + ((2 - 1)  << 0))
 #define DP_MFD_400     (3 - 1)
 #define DP_MFN_400     1
@@ -324,6 +331,8 @@
 #define BOARD_REV_1_0  0x0
 #define BOARD_REV_2_0  0x1
 
+#define BOARD_VER_OFFSET       0x8
+
 #define IMX_IIM_BASE   IIM_BASE_ADDR
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
@@ -464,6 +473,24 @@ struct src {
        u32     simr;
 };
 
+struct srtc_regs {
+       u32     lpscmr;         /* 0x00 */
+       u32     lpsclr;         /* 0x04 */
+       u32     lpsar;          /* 0x08 */
+       u32     lpsmcr;         /* 0x0c */
+       u32     lpcr;           /* 0x10 */
+       u32     lpsr;           /* 0x14 */
+       u32     lppdr;          /* 0x18 */
+       u32     lpgr;           /* 0x1c */
+       u32     hpcmr;          /* 0x20 */
+       u32     hpclr;          /* 0x24 */
+       u32     hpamr;          /* 0x28 */
+       u32     hpalr;          /* 0x2c */
+       u32     hpcr;           /* 0x30 */
+       u32     hpisr;          /* 0x34 */
+       u32     hpienr;         /* 0x38 */
+};
+
 /* CSPI registers */
 struct cspi_regs {
        u32 rxdata;
@@ -510,8 +537,6 @@ struct fuse_bank1_regs {
        u32     fuse15_31[0x11];
 };
 
-extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
-
 #endif /* __ASSEMBLER__*/
 
 #endif                         /* __ASM_ARCH_MX5_IMX_REGS_H__ */