/*
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+#define CCM_CCOSR 0x020c4060
+#define CCM_CCGR0 0x020C4068
+#define CCM_CCGR1 0x020C406c
+#define CCM_CCGR2 0x020C4070
+#define CCM_CCGR3 0x020C4074
+#define CCM_CCGR4 0x020C4078
+#define CCM_CCGR5 0x020C407c
+#define CCM_CCGR6 0x020C4080
+
+#define PMU_MISC2 0x020C8170
+
+#ifndef __ASSEMBLY__
struct mxc_ccm_reg {
u32 ccr; /* 0x0000 */
u32 ccdr;
u32 cs1cdr;
u32 cs2cdr;
u32 cdcdr; /* 0x0030 */
- u32 chscdr;
+ u32 chsccdr;
u32 cscdr2;
u32 cscdr3;
u32 cscdr4; /* 0x0040 */
u32 cmeor;
};
+struct anatop_regs {
+ mxs_reg_32(pll_arm); /* 0x000 */
+ mxs_reg_32(usb1_pll_480_ctrl); /* 0x010 */
+ mxs_reg_32(usb2_pll_480_ctrl); /* 0x020 */
+ mxs_reg_32(pll_528); /* 0x030 */
+ reg_32(pll_528_ss); /* 0x040 */
+ reg_32(pll_528_num); /* 0x050 */
+ reg_32(pll_528_denom); /* 0x060 */
+ mxs_reg_32(pll_audio); /* 0x070 */
+ reg_32(pll_audio_num); /* 0x080 */
+ reg_32(pll_audio_denom); /* 0x090 */
+ mxs_reg_32(pll_video); /* 0x0a0 */
+ reg_32(pll_video_num); /* 0x0b0 */
+ reg_32(pll_video_denom); /* 0x0c0 */
+ mxs_reg_32(pll_mlb); /* 0x0d0 */
+ mxs_reg_32(pll_enet); /* 0x0e0 */
+ mxs_reg_32(pfd_480); /* 0x0f0 */
+ mxs_reg_32(pfd_528); /* 0x100 */
+ mxs_reg_32(reg_1p1); /* 0x110 */
+ mxs_reg_32(reg_3p0); /* 0x120 */
+ mxs_reg_32(reg_2p5); /* 0x130 */
+ mxs_reg_32(reg_core); /* 0x140 */
+ mxs_reg_32(ana_misc0); /* 0x150 */
+ mxs_reg_32(ana_misc1); /* 0x160 */
+ mxs_reg_32(ana_misc2); /* 0x170 */
+ mxs_reg_32(tempsense0); /* 0x180 */
+ mxs_reg_32(tempsense1); /* 0x190 */
+ mxs_reg_32(usb1_vbus_detect); /* 0x1a0 */
+ mxs_reg_32(usb1_chrg_detect); /* 0x1b0 */
+ mxs_reg_32(usb1_vbus_det_stat); /* 0x1c0 */
+ mxs_reg_32(usb1_chrg_det_stat); /* 0x1d0 */
+ mxs_reg_32(usb1_loopback); /* 0x1e0 */
+ mxs_reg_32(usb1_misc); /* 0x1f0 */
+ mxs_reg_32(usb2_vbus_detect); /* 0x200 */
+ mxs_reg_32(usb2_chrg_detect); /* 0x210 */
+ mxs_reg_32(usb2_vbus_det_stat); /* 0x220 */
+ mxs_reg_32(usb2_chrg_det_stat); /* 0x230 */
+ mxs_reg_32(usb2_loopback); /* 0x240 */
+ mxs_reg_32(usb2_misc); /* 0x250 */
+ reg_32(digprog); /* 0x260 */
+ reg_32(rsrvd); /* 0x270 */
+ reg_32(digprog_sololite); /* 0x280 */
+};
+#endif
+
/* Define the bits in register CCR */
#define MXC_CCM_CCR_RBC_EN (1 << 27)
#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
+#ifdef CONFIG_MX6SL
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
+#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
+#else
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
+#endif
+#define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET 6
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
/* Define the bits in register CS1CDR */
/* Define the bits in register CS2CDR */
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
/* Define the bits in registers CCGRx */
#define MXC_CCM_CCGR_CG_MASK 3
-#define MXC_CCM_CCGR0_CG14_OFFSET 28
-#define MXC_CCM_CCGR0_CG14_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG14_OFFSET)
-#define MXC_CCM_CCGR0_CG13_OFFSET 26
-#define MXC_CCM_CCGR0_CG13_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG13_OFFSET)
-#define MXC_CCM_CCGR0_CG12_OFFSET 24
-#define MXC_CCM_CCGR0_CG12_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG12_OFFSET)
-#define MXC_CCM_CCGR0_CG11_OFFSET 22
-#define MXC_CCM_CCGR0_CG11_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG11_OFFSET)
-#define MXC_CCM_CCGR0_CG10_OFFSET 20
-#define MXC_CCM_CCGR0_CG10_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG10_OFFSET)
-#define MXC_CCM_CCGR0_CG9_OFFSET 18
-#define MXC_CCM_CCGR0_CG9_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG9_OFFSET)
-#define MXC_CCM_CCGR0_CG8_OFFSET 16
-#define MXC_CCM_CCGR0_CG8_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG8_OFFSET)
-#define MXC_CCM_CCGR0_CG7_OFFSET 14
-#define MXC_CCM_CCGR0_CG6_OFFSET 12
-#define MXC_CCM_CCGR0_CG5_OFFSET 10
-#define MXC_CCM_CCGR0_CG5_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG5_OFFSET)
-#define MXC_CCM_CCGR0_CG4_OFFSET 8
-#define MXC_CCM_CCGR0_CG4_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG4_OFFSET)
-#define MXC_CCM_CCGR0_CG3_OFFSET 6
-#define MXC_CCM_CCGR0_CG3_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG3_OFFSET)
-#define MXC_CCM_CCGR0_CG2_OFFSET 4
-#define MXC_CCM_CCGR0_CG2_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG2_OFFSET)
-#define MXC_CCM_CCGR0_CG1_OFFSET 2
-#define MXC_CCM_CCGR0_CG1_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG1_OFFSET)
-#define MXC_CCM_CCGR0_CG0_OFFSET 0
-#define MXC_CCM_CCGR0_CG0_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET)
-
-#define MXC_CCM_CCGR0_DTCP_OFFSET MXC_CCM_CCGR0_CG14_OFFSET
-#define MXC_CCM_CCGR0_DCIC2_OFFSET MXC_CCM_CCGR0_CG13_OFFSET
-#define MXC_CCM_CCGR0_DCIC1_OFFSET MXC_CCM_CCGR0_CG12_OFFSET
-#define MXC_CCM_CCGR0_ARM_DBG_OFFSET MXC_CCM_CCGR0_CG11_OFFSET
-#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET MXC_CCM_CCGR0_CG10_OFFSET
-#define MXC_CCM_CCGR0_CAN2_OFFSET MXC_CCM_CCGR0_CG9_OFFSET
-#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET MXC_CCM_CCGR0_CG8_OFFSET
-#define MXC_CCM_CCGR0_CAN1_OFFSET MXC_CCM_CCGR0_CG7_OFFSET
-#define MXC_CCM_CCGR0_CAAM_IPG_OFFSET MXC_CCM_CCGR0_CG6_OFFSET
-#define MXC_CCM_CCGR0_CAAM_ACLK_OFFSET MXC_CCM_CCGR0_CG5_OFFSET
-#define MXC_CCM_CCGR0_CAAM_SEC_MEM_OFFSET MXC_CCM_CCGR0_CG4_OFFSET
-#define MXC_CCM_CCGR0_ASRC_OFFSET MXC_CCM_CCGR0_CG3_OFFSET
-#define MXC_CCM_CCGR0_APBHDMA_OFFSET MXC_CCM_CCGR0_CG2_OFFSET
-#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET MXC_CCM_CCGR0_CG1_OFFSET
-#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET MXC_CCM_CCGR0_CG0_OFFSET
-
-#define MXC_CCM_CCGR1_CG15_OFFSET 30
-#define MXC_CCM_CCGR1_CG14_OFFSET 28
-#define MXC_CCM_CCGR1_CG13_OFFSET 26
-#define MXC_CCM_CCGR1_CG12_OFFSET 24
-#define MXC_CCM_CCGR1_CG11_OFFSET 22
-#define MXC_CCM_CCGR1_CG10_OFFSET 20
-#define MXC_CCM_CCGR1_CG9_OFFSET 18
-#define MXC_CCM_CCGR1_CG8_OFFSET 16
-#define MXC_CCM_CCGR1_CG7_OFFSET 14
-#define MXC_CCM_CCGR1_CG6_OFFSET 12
-#define MXC_CCM_CCGR1_CG5_OFFSET 10
-#define MXC_CCM_CCGR1_CG4_OFFSET 8
-#define MXC_CCM_CCGR1_CG3_OFFSET 6
-#define MXC_CCM_CCGR1_CG2_OFFSET 4
-#define MXC_CCM_CCGR1_CG1_OFFSET 2
-#define MXC_CCM_CCGR1_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR1_GPU3D_OFFSET MXC_CCM_CCGR1_CG13_OFFSET
-#define MXC_CCM_CCGR1_GPU2D_OFFSET MXC_CCM_CCGR1_CG12_OFFSET
-#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET MXC_CCM_CCGR1_CG11_OFFSET
-#define MXC_CCM_CCGR1_GPT_OFFSET MXC_CCM_CCGR1_CG10_OFFSET
-#define MXC_CCM_CCGR1_ESAI_OFFSET MXC_CCM_CCGR1_CG8_OFFSET
-#define MXC_CCM_CCGR1_EPIT2_OFFSET MXC_CCM_CCGR1_CG7_OFFSET
-#define MXC_CCM_CCGR1_EPIT1_OFFSET MXC_CCM_CCGR1_CG6_OFFSET
-#define MXC_CCM_CCGR1_ENET_OFFSET MXC_CCM_CCGR1_CG5_OFFSET
-#define MXC_CCM_CCGR1_ECSPI5_OFFSET MXC_CCM_CCGR1_CG4_OFFSET
-#define MXC_CCM_CCGR1_ECSPI4_OFFSET MXC_CCM_CCGR1_CG3_OFFSET
-#define MXC_CCM_CCGR1_ECSPI3_OFFSET MXC_CCM_CCGR1_CG2_OFFSET
-#define MXC_CCM_CCGR1_ECSPI2_OFFSET MXC_CCM_CCGR1_CG1_OFFSET
-#define MXC_CCM_CCGR1_ECSPI1_OFFSET MXC_CCM_CCGR1_CG0_OFFSET
-
-#define MXC_CCM_CCGR2_CG13_OFFSET 26
-#define MXC_CCM_CCGR2_CG12_OFFSET 24
-#define MXC_CCM_CCGR2_CG11_OFFSET 22
-#define MXC_CCM_CCGR2_CG10_OFFSET 20
-#define MXC_CCM_CCGR2_CG9_OFFSET 18
-#define MXC_CCM_CCGR2_CG8_OFFSET 16
-#define MXC_CCM_CCGR2_CG7_OFFSET 14
-#define MXC_CCM_CCGR2_CG6_OFFSET 12
-#define MXC_CCM_CCGR2_CG6_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR2_CG6_OFFSET)
-#define MXC_CCM_CCGR2_CG5_OFFSET 10
-#define MXC_CCM_CCGR2_CG4_OFFSET 8
-#define MXC_CCM_CCGR2_CG3_OFFSET 6
-#define MXC_CCM_CCGR2_CG2_OFFSET 4
-#define MXC_CCM_CCGR2_CG1_OFFSET 2
-#define MXC_CCM_CCGR2_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_OFFSET MXC_CCM_CCGR2_CG13_OFFSET
-#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_TZASC2_OFFSET MXC_CCM_CCGR2_CG12_OFFSET
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1__OFFSET MXC_CCM_CCGR2_CG11_OFFSET
-#define MXC_CCM_CCGR2_IPMUX3_OFFSET MXC_CCM_CCGR2_CG10_OFFSET
-#define MXC_CCM_CCGR2_IPMUX2_OFFSET MXC_CCM_CCGR2_CG9_OFFSET
-#define MXC_CCM_CCGR2_IPMUX1_OFFSET MXC_CCM_CCGR2_CG8_OFFSET
-#define MXC_CCM_CCGR2_IOMUX_IPT_OFFSET MXC_CCM_CCGR2_CG7_OFFSET
-#define MXC_CCM_CCGR2_OCOTP_OFFSET MXC_CCM_CCGR2_CG6_OFFSET
-#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET MXC_CCM_CCGR2_CG5_OFFSET
-#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET MXC_CCM_CCGR2_CG4_OFFSET
-#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET MXC_CCM_CCGR2_CG3_OFFSET
-#define MXC_CCM_CCGR2_HDMI_TX_ISFR_OFFSET MXC_CCM_CCGR2_CG2_OFFSET
-#define MXC_CCM_CCGR2_HDMI_TX_IAHB_OFFSET MXC_CCM_CCGR2_CG0_OFFSET
-
-#define MXC_CCM_CCGR3_CG15_OFFSET 30
-#define MXC_CCM_CCGR3_CG14_OFFSET 28
-#define MXC_CCM_CCGR3_CG13_OFFSET 26
-#define MXC_CCM_CCGR3_CG12_OFFSET 24
-#define MXC_CCM_CCGR3_CG11_OFFSET 22
-#define MXC_CCM_CCGR3_CG10_OFFSET 20
-#define MXC_CCM_CCGR3_CG9_OFFSET 18
-#define MXC_CCM_CCGR3_CG8_OFFSET 16
-#define MXC_CCM_CCGR3_CG7_OFFSET 14
-#define MXC_CCM_CCGR3_CG6_OFFSET 12
-#define MXC_CCM_CCGR3_CG5_OFFSET 10
-#define MXC_CCM_CCGR3_CG4_OFFSET 8
-#define MXC_CCM_CCGR3_CG3_OFFSET 6
-#define MXC_CCM_CCGR3_CG2_OFFSET 4
-#define MXC_CCM_CCGR3_CG1_OFFSET 2
-#define MXC_CCM_CCGR3_CG0_OFFSET 0
-#define MXC_CCM_CCGR3_CG0_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR3_CG0_OFFSET)
-
-#define MXC_CCM_CCGR3_OPENVGAXI_OFFSET MXC_CCM_CCGR3_CG15_OFFSET
-#define MXC_CCM_CCGR3_OCRAM_OFFSET MXC_CCM_CCGR3_CG14_OFFSET
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_P1_OFFSET MXC_CCM_CCGR3_CG13_OFFSET
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_P0_OFFSET MXC_CCM_CCGR3_CG12_OFFSET
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_P1_OFFSET MXC_CCM_CCGR3_CG11_OFFSET
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_P0_OFFSET MXC_CCM_CCGR3_CG10_OFFSET
-#define MXC_CCM_CCGR3_MLB_OFFSET MXC_CCM_CCGR3_CG9_OFFSET
-#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET MXC_CCM_CCGR3_CG8_OFFSET
-#define MXC_CCM_CCGR3_LDB_DI1_OFFSET MXC_CCM_CCGR3_CG7_OFFSET
-#define MXC_CCM_CCGR3_LDB_DI0_OFFSET MXC_CCM_CCGR3_CG6_OFFSET
-#define MXC_CCM_CCGR3_IPU2_DI1_OFFSET MXC_CCM_CCGR3_CG5_OFFSET
-#define MXC_CCM_CCGR3_IPU2_DI0_OFFSET MXC_CCM_CCGR3_CG4_OFFSET
-#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET MXC_CCM_CCGR3_CG3_OFFSET
-#define MXC_CCM_CCGR3_IPU1_DI1_OFFSET MXC_CCM_CCGR3_CG2_OFFSET
-#define MXC_CCM_CCGR3_IPU1_DI0_OFFSET MXC_CCM_CCGR3_CG1_OFFSET
-#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET MXC_CCM_CCGR3_CG0_OFFSET
-
-#define MXC_CCM_CCGR4_CG15_OFFSET 30
-#define MXC_CCM_CCGR4_CG14_OFFSET 28
-#define MXC_CCM_CCGR4_CG13_OFFSET 26
-#define MXC_CCM_CCGR4_CG12_OFFSET 24
-#define MXC_CCM_CCGR4_CG11_OFFSET 22
-#define MXC_CCM_CCGR4_CG10_OFFSET 20
-#define MXC_CCM_CCGR4_CG9_OFFSET 18
-#define MXC_CCM_CCGR4_CG8_OFFSET 16
-#define MXC_CCM_CCGR4_CG7_OFFSET 14
-#define MXC_CCM_CCGR4_CG6_OFFSET 12
-#define MXC_CCM_CCGR4_CG5_OFFSET 10
-#define MXC_CCM_CCGR4_CG4_OFFSET 8
-#define MXC_CCM_CCGR4_CG3_OFFSET 6
-#define MXC_CCM_CCGR4_CG2_OFFSET 4
-#define MXC_CCM_CCGR4_CG1_OFFSET 2
-#define MXC_CCM_CCGR4_CG0_OFFSET 0
-
-#if 0
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG15_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG14_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG13_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG12_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG11_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG10_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG9_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG8_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG7_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG6_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG5_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG4_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG3_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG2_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG1_OFFSET
-#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG0_OFFSET
-#endif
-
-#define MXC_CCM_CCGR5_CG15_OFFSET 30
-#define MXC_CCM_CCGR5_CG14_OFFSET 28
-#define MXC_CCM_CCGR5_CG14_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG14_OFFSET)
-#define MXC_CCM_CCGR5_CG13_OFFSET 26
-#define MXC_CCM_CCGR5_CG13_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG13_OFFSET)
-#define MXC_CCM_CCGR5_CG12_OFFSET 24
-#define MXC_CCM_CCGR5_CG12_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG12_OFFSET)
-#define MXC_CCM_CCGR5_CG11_OFFSET 22
-#define MXC_CCM_CCGR5_CG11_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG11_OFFSET)
-#define MXC_CCM_CCGR5_CG10_OFFSET 20
-#define MXC_CCM_CCGR5_CG10_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG10_OFFSET)
-#define MXC_CCM_CCGR5_CG9_OFFSET 18
-#define MXC_CCM_CCGR5_CG9_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG9_OFFSET)
-#define MXC_CCM_CCGR5_CG8_OFFSET 16
-#define MXC_CCM_CCGR5_CG8_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG8_OFFSET)
-#define MXC_CCM_CCGR5_CG7_OFFSET 14
-#define MXC_CCM_CCGR5_CG7_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG7_OFFSET)
-#define MXC_CCM_CCGR5_CG6_OFFSET 12
-#define MXC_CCM_CCGR5_CG6_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG6_OFFSET)
-#define MXC_CCM_CCGR5_CG5_OFFSET 10
-#define MXC_CCM_CCGR5_CG4_OFFSET 8
-#define MXC_CCM_CCGR5_CG3_OFFSET 6
-#define MXC_CCM_CCGR5_CG2_OFFSET 4
-#define MXC_CCM_CCGR5_CG2_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG2_OFFSET)
-#define MXC_CCM_CCGR5_CG1_OFFSET 2
-#define MXC_CCM_CCGR5_CG0_OFFSET 0
-
-#if 0
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG15_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG14_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG13_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG12_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG11_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG10_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG9_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG8_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG7_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG6_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG5_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG4_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG3_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG1_OFFSET
-#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG0_OFFSET
-#endif
-#define MXC_CCM_CCGR5_SATA_MASK MXC_CCM_CCGR5_CG2_MASK
-
-#define MXC_CCM_CCGR6_CG15_OFFSET 30
-#define MXC_CCM_CCGR6_CG14_OFFSET 28
-#define MXC_CCM_CCGR6_CG14_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG14_OFFSET)
-#define MXC_CCM_CCGR6_CG13_OFFSET 26
-#define MXC_CCM_CCGR6_CG13_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG13_OFFSET)
-#define MXC_CCM_CCGR6_CG12_OFFSET 24
-#define MXC_CCM_CCGR6_CG12_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG12_OFFSET)
-#define MXC_CCM_CCGR6_CG11_OFFSET 22
-#define MXC_CCM_CCGR6_CG11_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG11_OFFSET)
-#define MXC_CCM_CCGR6_CG10_OFFSET 20
-#define MXC_CCM_CCGR6_CG10_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG10_OFFSET)
-#define MXC_CCM_CCGR6_CG9_OFFSET 18
-#define MXC_CCM_CCGR6_CG9_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG9_OFFSET)
-#define MXC_CCM_CCGR6_CG8_OFFSET 16
-#define MXC_CCM_CCGR6_CG8_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG8_OFFSET)
-#define MXC_CCM_CCGR6_CG7_OFFSET 14
-#define MXC_CCM_CCGR6_CG7_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG7_OFFSET)
-#define MXC_CCM_CCGR6_CG6_OFFSET 12
-#define MXC_CCM_CCGR6_CG6_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG6_OFFSET)
-#define MXC_CCM_CCGR6_CG5_OFFSET 10
-#define MXC_CCM_CCGR6_CG4_OFFSET 8
-#define MXC_CCM_CCGR6_CG3_OFFSET 6
-#define MXC_CCM_CCGR6_CG2_OFFSET 4
-#define MXC_CCM_CCGR6_CG2_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG2_OFFSET)
-#define MXC_CCM_CCGR6_CG1_OFFSET 2
-#define MXC_CCM_CCGR6_CG1_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG1_OFFSET)
-#define MXC_CCM_CCGR6_CG0_OFFSET 0
-#define MXC_CCM_CCGR6_CG0_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG0_OFFSET)
-
-#if 0
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG15_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG14_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG13_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG12_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG11_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG10_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG9_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG8_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG7_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG6_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG5_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG4_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG3_OFFSET
-#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG2_OFFSET
-#endif
-#define MXC_CCM_CCGR6_USDHC1_MASK MXC_CCM_CCGR6_CG1_MASK
-#define MXC_CCM_CCGR6_USBOH3_MASK MXC_CCM_CCGR6_CG0_MASK
-
-#define MXC_CCM_CCGR7_CG15_OFFSET 30
-#define MXC_CCM_CCGR7_CG14_OFFSET 28
-#define MXC_CCM_CCGR7_CG14_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG14_OFFSET)
-#define MXC_CCM_CCGR7_CG13_OFFSET 26
-#define MXC_CCM_CCGR7_CG13_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG13_OFFSET)
-#define MXC_CCM_CCGR7_CG12_OFFSET 24
-#define MXC_CCM_CCGR7_CG12_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG12_OFFSET)
-#define MXC_CCM_CCGR7_CG11_OFFSET 22
-#define MXC_CCM_CCGR7_CG11_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG11_OFFSET)
-#define MXC_CCM_CCGR7_CG10_OFFSET 20
-#define MXC_CCM_CCGR7_CG10_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG10_OFFSET)
-#define MXC_CCM_CCGR7_CG9_OFFSET 18
-#define MXC_CCM_CCGR7_CG9_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG9_OFFSET)
-#define MXC_CCM_CCGR7_CG8_OFFSET 16
-#define MXC_CCM_CCGR7_CG8_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG8_OFFSET)
-#define MXC_CCM_CCGR7_CG7_OFFSET 14
-#define MXC_CCM_CCGR7_CG7_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG7_OFFSET)
-#define MXC_CCM_CCGR7_CG6_OFFSET 12
-#define MXC_CCM_CCGR7_CG6_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG6_OFFSET)
-#define MXC_CCM_CCGR7_CG5_OFFSET 10
-#define MXC_CCM_CCGR7_CG4_OFFSET 8
-#define MXC_CCM_CCGR7_CG3_OFFSET 6
-#define MXC_CCM_CCGR7_CG2_OFFSET 4
-#define MXC_CCM_CCGR7_CG2_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG2_OFFSET)
-#define MXC_CCM_CCGR7_CG1_OFFSET 2
-#define MXC_CCM_CCGR7_CG0_OFFSET 0
-
-#if 0
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG15_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG14_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG13_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG12_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG11_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG10_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG9_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG8_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG7_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG6_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG5_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG4_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG3_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG2_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG1_OFFSET
-#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG0_OFFSET
-#endif
-
-struct anatop_regs {
- mx6_reg_32(pll_arm); /* 0x000 */
- mx6_reg_32(usb1_pll_480_ctrl); /* 0x010 */
- mx6_reg_32(usb2_pll_480_ctrl); /* 0x020 */
- mx6_reg_32(pll_528); /* 0x030 */
- reg_32(pll_528_ss); /* 0x040 */
- reg_32(pll_528_num); /* 0x050 */
- reg_32(pll_528_denom); /* 0x060 */
- mx6_reg_32(pll_audio); /* 0x070 */
- reg_32(pll_audio_num); /* 0x080 */
- reg_32(pll_audio_denom); /* 0x090 */
- mx6_reg_32(pll_video); /* 0x0a0 */
- reg_32(pll_video_num); /* 0x0b0 */
- reg_32(pll_video_denom); /* 0x0c0 */
- mx6_reg_32(pll_mlb); /* 0x0d0 */
- mx6_reg_32(pll_enet); /* 0x0e0 */
- mx6_reg_32(pfd_480); /* 0x0f0 */
- mx6_reg_32(pfd_528); /* 0x100 */
- mx6_reg_32(reg_1p1); /* 0x110 */
- mx6_reg_32(reg_3p0); /* 0x120 */
- mx6_reg_32(reg_2p5); /* 0x130 */
- mx6_reg_32(reg_core); /* 0x140 */
- mx6_reg_32(ana_misc0); /* 0x150 */
- mx6_reg_32(ana_misc1); /* 0x160 */
- mx6_reg_32(ana_misc2); /* 0x170 */
- mx6_reg_32(tempsense0); /* 0x180 */
- mx6_reg_32(tempsense1); /* 0x190 */
- mx6_reg_32(usb1_vbus_detect); /* 0x1a0 */
- mx6_reg_32(usb1_chrg_detect); /* 0x1b0 */
- mx6_reg_32(usb1_vbus_det_stat); /* 0x1c0 */
- mx6_reg_32(usb1_chrg_det_stat); /* 0x1d0 */
- mx6_reg_32(usb1_loopback); /* 0x1e0 */
- mx6_reg_32(usb1_misc); /* 0x1f0 */
- mx6_reg_32(usb2_vbus_detect); /* 0x200 */
- mx6_reg_32(usb2_chrg_detect); /* 0x210 */
- mx6_reg_32(usb2_vbus_det_stat); /* 0x220 */
- mx6_reg_32(usb2_chrg_det_stat); /* 0x230 */
- mx6_reg_32(usb2_loopback); /* 0x240 */
- mx6_reg_32(usb2_misc); /* 0x250 */
- reg_32(digprog); /* 0x260 */
- reg_32(rsrvd); /* 0x270 */
- reg_32(digprog_sololite); /* 0x280 */
-};
-
-#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
-#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD0_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
-#define ANATOP_PFD_480_PFD0_STABLE_MASK (1 << ANATOP_PFD_480_PFD0_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
-#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1 << ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
-#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD1_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
-#define ANATOP_PFD_480_PFD1_STABLE_MASK (1 << ANATOP_PFD_480_PFD1_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
-#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
-#define ANATOP_PFD_480_PFD2_FRAC_MASK (1 << ANATOP_PFD_480_PFD2_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
-#define ANATOP_PFD_480_PFD2_STABLE_MASK (1 << ANATOP_PFD_480_PFD2_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
-#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
-#define ANATOP_PFD_480_PFD3_FRAC_MASK (1 << ANATOP_PFD_480_PFD3_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
-#define ANATOP_PFD_480_PFD3_STABLE_MASK (1 << ANATOP_PFD_480_PFD3_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
-
-#define BM_ANADIG_PLL_ARM_LOCK (1 << 31)
-#define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19)
-#define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18)
-#define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17)
-#define BM_ANADIG_PLL_ARM_BYPASS (1 << 16)
-#define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
+#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
+#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
+#define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
+#define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
+#define MXC_CCM_CCGR0_ASRC_OFFSET 6
+#define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_OFFSET 14
+#define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
+#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_OFFSET 18
+#define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
+#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
+#define MXC_CCM_CCGR0_DCIC1_OFFSET 24
+#define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
+#define MXC_CCM_CCGR0_DCIC2_OFFSET 26
+#define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
+#define MXC_CCM_CCGR0_DTCP_OFFSET 28
+#define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
+
+#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
+#define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
+#define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
+#define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
+#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
+#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
+#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
+#define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
+#define MXC_CCM_CCGR1_ESAIS_OFFSET 16
+#define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
+#define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
+#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_GPU2D_OFFSET 24
+#define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
+#define MXC_CCM_CCGR1_GPU3D_OFFSET 26
+#define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
+
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
+#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
+#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
+#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
+#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
+#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
+#define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
+#define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
+#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+
+#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
+#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
+#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
+#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
+#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
+#define MXC_CCM_CCGR3_MLB_OFFSET 18
+#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
+#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
+#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
+#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
+
+#define MXC_CCM_CCGR4_PCIE_OFFSET 0
+#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR4_PWM1_OFFSET 16
+#define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
+#define MXC_CCM_CCGR4_PWM2_OFFSET 18
+#define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
+#define MXC_CCM_CCGR4_PWM3_OFFSET 20
+#define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
+#define MXC_CCM_CCGR4_PWM4_OFFSET 22
+#define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
+
+#define MXC_CCM_CCGR5_ROM_OFFSET 0
+#define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
+#define MXC_CCM_CCGR5_SATA_OFFSET 4
+#define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
+#define MXC_CCM_CCGR5_SDMA_OFFSET 6
+#define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_OFFSET 12
+#define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_OFFSET 14
+#define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_OFFSET 18
+#define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_OFFSET 20
+#define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_OFFSET 22
+#define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_UART_OFFSET 24
+#define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+
+#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
+#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
+#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
+#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
+#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
+#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+
+#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
+#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD0_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
+#define ANATOP_PFD_480_PFD0_STABLE_MASK (1 << ANATOP_PFD_480_PFD0_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
+#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1 << ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
+#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD1_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
+#define ANATOP_PFD_480_PFD1_STABLE_MASK (1 << ANATOP_PFD_480_PFD1_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
+#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
+#define ANATOP_PFD_480_PFD2_FRAC_MASK (1 << ANATOP_PFD_480_PFD2_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
+#define ANATOP_PFD_480_PFD2_STABLE_MASK (1 << ANATOP_PFD_480_PFD2_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
+#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
+#define ANATOP_PFD_480_PFD3_FRAC_MASK (1 << ANATOP_PFD_480_PFD3_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
+#define ANATOP_PFD_480_PFD3_STABLE_MASK (1 << ANATOP_PFD_480_PFD3_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
+
+#define BM_ANADIG_PLL_ARM_LOCK (1 << 31)
+#define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19)
+#define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18)
+#define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17)
+#define BM_ANADIG_PLL_ARM_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \
(((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(0)
-#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(1)
-#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(2)
-#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(3)
-#define BM_ANADIG_PLL_ARM_ENABLE (1 << 13)
-#define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12)
-#define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9)
-#define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7)
-#define BP_ANADIG_PLL_ARM_DIV_SELECT 0
-#define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(0)
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(1)
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(2)
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(3)
+#define BM_ANADIG_PLL_ARM_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_ARM_DIV_SELECT 0
+#define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
#define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \
(((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
BM_ANADIG_PLL_ARM_DIV_SELECT)
-#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK (1 << 31)
-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS (1 << 16)
-#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK (1 << 31)
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS (1 << 16)
+#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
(((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) & \
BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(1)
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(2)
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(3)
-#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE (1 << 13)
-#define BM_ANADIG_USB1_PLL_480_CTRL_POWER (1 << 12)
-#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP (1 << 9)
-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF (1 << 7)
-#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
-#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
-#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE (1 << 13)
+#define BM_ANADIG_USB1_PLL_480_CTRL_POWER (1 << 12)
+#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP (1 << 9)
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF (1 << 7)
+#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
+#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
+#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
(((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) & \
BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
-#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
-#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
+#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
(((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) & \
BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
-#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK (1 << 31)
-#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS (1 << 16)
-#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 14
-#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK (1 << 31)
+#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS (1 << 16)
+#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 14
+#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
#define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
(((v) << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) & \
BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(1)
#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(2)
#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(3)
-#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE (1 << 13)
-#define BM_ANADIG_USB2_PLL_480_CTRL_POWER (1 << 12)
-#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP (1 << 9)
-#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF (1 << 7)
-#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
-#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0 2
-#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
+#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE (1 << 13)
+#define BM_ANADIG_USB2_PLL_480_CTRL_POWER (1 << 12)
+#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP (1 << 9)
+#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF (1 << 7)
+#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
+#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0 2
+#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
#define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v) \
(((v) << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0) & \
BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
-#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0
-#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
+#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0
+#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v) \
(((v) << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) & \
BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
-#define BM_ANADIG_PLL_SYS_LOCK (1 << 31)
-#define BM_ANADIG_PLL_SYS_PLL_SEL (1 << 19)
-#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL (1 << 18)
-#define BM_ANADIG_PLL_SYS_LVDS_SEL (1 << 17)
-#define BM_ANADIG_PLL_SYS_BYPASS (1 << 16)
-#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
+#define BM_ANADIG_PLL_SYS_LOCK (1 << 31)
+#define BM_ANADIG_PLL_SYS_PLL_SEL (1 << 19)
+#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL (1 << 18)
+#define BM_ANADIG_PLL_SYS_LVDS_SEL (1 << 17)
+#define BM_ANADIG_PLL_SYS_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
(((v) << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_SYS_ENABLE (1 << 13)
-#define BM_ANADIG_PLL_SYS_POWERDOWN (1 << 12)
-#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_PLL_SYS_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_PLL_SYS_HALF_CP (1 << 9)
-#define BM_ANADIG_PLL_SYS_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_PLL_SYS_HALF_LF (1 << 7)
-#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
-#define BM_ANADIG_PLL_SYS_DIV_SELECT (0x7F << BP_ANADIG_PLL_SYS_DIV_SELECT)
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_SYS_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_SYS_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_SYS_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_SYS_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_SYS_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_SYS_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
+#define BM_ANADIG_PLL_SYS_DIV_SELECT (0x7F << BP_ANADIG_PLL_SYS_DIV_SELECT)
#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
(((v) << BP_ANADIG_PLL_SYS_DIV_SELECT) & BM_ANADIG_PLL_SYS_DIV_SELECT)
-#define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
-#define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
-#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
+#define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
+#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
+#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
(((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
-#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
-#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
-#define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
-#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
(((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
-#define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
-#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
-#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
-#define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
(((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
-#define BP_ANADIG_PLL_AUDIO_NUM_A 0
-#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
+#define BP_ANADIG_PLL_AUDIO_NUM_A 0
+#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
(((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & BM_ANADIG_PLL_AUDIO_NUM_A)
-#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
-#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
+#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
+#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
(((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & BM_ANADIG_PLL_AUDIO_DENOM_B)
-#define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
-#define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
+#define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
+#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
+#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
(((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
-#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
-#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
-#define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
-#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
(((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
-#define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
-#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
-#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
-#define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
(((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
-#define BP_ANADIG_PLL_VIDEO_NUM_A 0
-#define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
+#define BP_ANADIG_PLL_VIDEO_NUM_A 0
+#define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
(((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & BM_ANADIG_PLL_VIDEO_NUM_A)
-#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
-#define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
+#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
+#define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
(((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & BM_ANADIG_PLL_VIDEO_DENOM_B)
-#define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
-#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
-#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+#define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
+#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
+#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
(((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
-#define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
-#define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
+#define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
(((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
-#define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
-#define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
+#define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
(((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
-#define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
-#define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
+#define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
(((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
-#define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
-#define BP_ANADIG_PLL_MLB_PHASE_SEL 12
-#define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
+#define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_MLB_PHASE_SEL 12
+#define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
(((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & BM_ANADIG_PLL_MLB_PHASE_SEL)
-#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
-
-#define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
-#define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
-#define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
-#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
-#define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
-#define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
-#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
+
+#define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
+#define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
(((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
-#define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
-#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
-#define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
-#define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
-#define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
-#define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
-#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
-#define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
+#define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
(((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & BM_ANADIG_PLL_ENET_DIV_SELECT)
-#define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
-#define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
-#define BP_ANADIG_PFD_480_PFD3_FRAC 24
-#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
+#define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
+#define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
+#define BP_ANADIG_PFD_480_PFD3_FRAC 24
+#define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
(((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & BM_ANADIG_PFD_480_PFD3_FRAC)
-#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
-#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
-#define BP_ANADIG_PFD_480_PFD2_FRAC 16
-#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
-#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
- (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & BM_ANADIG_PFD_480_PFD2_FRAC)
-#define BM_ANADIG_PFD_480_PFD1_CLKGATE (1 << 15)
-#define BM_ANADIG_PFD_480_PFD1_STABLE (1 << 14)
-#define BP_ANADIG_PFD_480_PFD1_FRAC 8
-#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
-#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
- (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & BM_ANADIG_PFD_480_PFD1_FRAC)
-#define BM_ANADIG_PFD_480_PFD0_CLKGATE (1 << 7)
-#define BM_ANADIG_PFD_480_PFD0_STABLE (1 << 6)
-#define BP_ANADIG_PFD_480_PFD0_FRAC 0
-#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
-#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
- (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & BM_ANADIG_PFD_480_PFD0_FRAC)
-
-#define BM_ANADIG_PFD_528_PFD3_CLKGATE (1 << 31)
-#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
-#define BP_ANADIG_PFD_528_PFD3_FRAC 24
-#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
-#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
- (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
-#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
-#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
-#define BP_ANADIG_PFD_528_PFD2_FRAC 16
-#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
-#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
- (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
-#define BM_ANADIG_PFD_528_PFD1_CLKGATE (1 << 15)
-#define BM_ANADIG_PFD_528_PFD1_STABLE (1 << 14)
-#define BP_ANADIG_PFD_528_PFD1_FRAC 8
-#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
-#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
- (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
-#define BM_ANADIG_PFD_528_PFD0_CLKGATE (1 << 7)
-#define BM_ANADIG_PFD_528_PFD0_STABLE (1 << 6)
-#define BP_ANADIG_PFD_528_PFD0_FRAC 0
-#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
-#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
- (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26
#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
projects / karo-tx-uboot.git / blobdiff