Merge branch 'master' of git://git.denx.de/u-boot-spi

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index fb0c4c76eb7b4580e9a536ac223af6f3586517e1..1f19727b581bd7c08b6141ec4d37bac4d8fb6c3c 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -53,6 +53,7 @@
 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
+#define L2_PL310_BASE                  0x00A02000
 #define GPV0_BASE_ADDR                  0x00B00000
 #define GPV1_BASE_ADDR                  0x00C00000
 #define PCIE_ARB_BASE_ADDR              0x01000000
@@ -245,6 +246,10 @@ struct src {
        u32     gpr10;
 };
 
+/* GPR1 bitfields */
+#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET                21
+#define IOMUXC_GPR1_ENET_CLK_SEL_MASK          (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+
 /* GPR3 bitfields */
 #define IOMUXC_GPR3_GPU_DBG_OFFSET             29
 #define IOMUXC_GPR3_GPU_DBG_MASK               (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
@@ -401,10 +406,11 @@ struct cspi_regs {
 #define MXC_CSPICTRL_CHAN      18
 
 /* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL                4
-#define MXC_CSPICON_PHA                0
-#define MXC_CSPICON_SSPOL      12
-#ifdef CONFIG_MX6SL
+#define MXC_CSPICON_PHA                0  /* SCLK phase control */
+#define MXC_CSPICON_POL                4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL      12 /* SS polarity */
+#define MXC_CSPICON_CTL                20 /* inactive state of SCLK */
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
 #define MXC_SPI_BASE_ADDRESSES \
        ECSPI1_BASE_ADDR, \
        ECSPI2_BASE_ADDR, \
@@ -659,28 +665,5 @@ struct wdog_regs {
        u16     wmcr;   /* Miscellaneous Control */
 };
 
-struct gpc_regs {
-       u32     ctrl;           /* 0x000 */
-       u32     pgr;            /* 0x004 */
-       u32     imr1;           /* 0x008 */
-       u32     imr2;           /* 0x00c */
-       u32     imr3;           /* 0x010 */
-       u32     imr4;           /* 0x014 */
-       u32     isr1;           /* 0x018 */
-       u32     isr2;           /* 0x01c */
-       u32     isr3;           /* 0x020 */
-       u32     isr4;           /* 0x024 */
-       u32     reserved1[0x86];
-       u32     gpu_ctrl;       /* 0x260 */
-       u32     gpu_pupscr;     /* 0x264 */
-       u32     gpu_pdnscr;     /* 0x268 */
-       u32     gpu_sr;         /* 0x26c */
-       u32     reserved2[0xc];
-       u32     cpu_ctrl;       /* 0x2a0 */
-       u32     cpu_pupscr;     /* 0x2a4 */
-       u32     cpu_pdnscr;     /* 0x2a8 */
-       u32     cpu_sr;         /* 0x2ac */
-};
-
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */