mxs_gpio: correctly use the GPIO API

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mxs / iomux.h

diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h
index 7abdf58b8bb7c92fadcbfdb4f609b1dee3ee28d2..a1d9016d5d80c2dc12a8394ac936099b285d4660 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/iomux.h
+++ b/arch/arm/include/asm/arch-mxs/iomux.h
@@ -3,24 +3,16 @@
  *                     <armlinux@phytec.de>
  * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __MACH_MXS_IOMUX_H__
 #define __MACH_MXS_IOMUX_H__
 
+#ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
 /*
  * IOMUX/PAD Bit field definitions
  *
@@ -33,44 +25,60 @@
  * PAD_VOL_VALID:      14      (1)
  * PAD_PULL:           15      (1)
  * PAD_PULL_VALID:     16      (1)
- * RESERVED:           17..31  (15)
+ * RESERVED:           17..30  (14)
+ * sentinel to produce an invalid GPIO number when using an
+ * iomux_cfg_t value where a plain GPIO number is expected
+ * GPIO_SENTINEL:      31      (1)
  */
+#ifdef CONFIG_MXS_IOMUX_COMPILE_CHECK
+typedef u64 iomux_cfg_t;
+#define IOMUX_CFG_SHIFT                32
+#else
 typedef u32 iomux_cfg_t;
+#define IOMUX_CFG_SHIFT                0
+#endif
 
-#define MXS_PAD_BANK_SHIFT     0
+#define MXS_PAD_BANK_SHIFT     (IOMUX_CFG_SHIFT + 0)
 #define MXS_PAD_BANK_MASK      ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
-#define MXS_PAD_PIN_SHIFT      3
+#define MXS_PAD_PIN_SHIFT      (IOMUX_CFG_SHIFT + 3)
 #define MXS_PAD_PIN_MASK       ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
-#define MXS_PAD_MUXSEL_SHIFT   8
+#define MXS_PAD_MUXSEL_SHIFT   (IOMUX_CFG_SHIFT + 8)
 #define MXS_PAD_MUXSEL_MASK    ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
-#define MXS_PAD_MA_SHIFT       10
+#define MXS_PAD_MA_SHIFT       (IOMUX_CFG_SHIFT + 10)
 #define MXS_PAD_MA_MASK                ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
-#define MXS_PAD_MA_VALID_SHIFT 12
+#define MXS_PAD_MA_VALID_SHIFT (IOMUX_CFG_SHIFT + 12)
 #define MXS_PAD_MA_VALID_MASK  ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
-#define MXS_PAD_VOL_SHIFT      13
+#define MXS_PAD_VOL_SHIFT      (IOMUX_CFG_SHIFT + 13)
 #define MXS_PAD_VOL_MASK       ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
-#define MXS_PAD_VOL_VALID_SHIFT        14
+#define MXS_PAD_VOL_VALID_SHIFT        (IOMUX_CFG_SHIFT + 14)
 #define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
-#define MXS_PAD_PULL_SHIFT     15
+#define MXS_PAD_PULL_SHIFT     (IOMUX_CFG_SHIFT + 15)
 #define MXS_PAD_PULL_MASK      ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
-#define MXS_PAD_PULL_VALID_SHIFT 16
+#define MXS_PAD_PULL_VALID_SHIFT (IOMUX_CFG_SHIFT + 16)
 #define MXS_PAD_PULL_VALID_MASK        ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
 
-#define PAD_MUXSEL_0           0
-#define PAD_MUXSEL_1           1
-#define PAD_MUXSEL_2           2
-#define PAD_MUXSEL_GPIO                3
+#define MXS_GPIO_SENTINEL_SHIFT        (IOMUX_CFG_SHIFT + 31)
+#define MXS_GPIO_SENTINEL_MASK ((iomux_cfg_t)0x1 << MXS_GPIO_SENTINEL_SHIFT)
 
-#define PAD_4MA                        0
-#define PAD_8MA                        1
-#define PAD_12MA               2
-#define PAD_16MA               3
+#define PAD_MUXSEL_0           (iomux_cfg_t)0
+#define PAD_MUXSEL_1           (iomux_cfg_t)1
+#define PAD_MUXSEL_2           (iomux_cfg_t)2
+#define PAD_MUXSEL_GPIO                (iomux_cfg_t)3
 
-#define PAD_1V8                        0
-#define PAD_3V3                        1
+#define PAD_4MA                        (iomux_cfg_t)0
+#define PAD_8MA                        (iomux_cfg_t)1
+#define PAD_12MA               (iomux_cfg_t)2
+#define PAD_16MA               (iomux_cfg_t)3
 
-#define PAD_NOPULL             0
-#define PAD_PULLUP             1
+#define PAD_1V8                        (iomux_cfg_t)0
+#if defined(CONFIG_SOC_MX28)
+#define PAD_3V3                        (iomux_cfg_t)1
+#else
+#define PAD_3V3                        (iomux_cfg_t)0
+#endif
+
+#define PAD_NOPULL             (iomux_cfg_t)0
+#define PAD_PULLUP             (iomux_cfg_t)1
 
 #define MXS_PAD_4MA    ((PAD_4MA << MXS_PAD_MA_SHIFT) | \
                                        MXS_PAD_MA_VALID_MASK)
@@ -100,7 +108,13 @@ typedef u32 iomux_cfg_t;
                ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) |      \
                ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) |              \
                ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) |            \
-               ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
+               ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT) |          \
+               ((iomux_cfg_t)1 << 31))
+
+#define MXS_PAD_TO_GPIO(p)     ((unsigned)(((((p) & MXS_PAD_BANK_MASK) >> \
+                                       MXS_PAD_BANK_SHIFT) << 5) |     \
+                                       ((p) & MXS_PAD_PIN_MASK) >>     \
+                                       MXS_PAD_PIN_SHIFT))
 
 /*
  * A pad becomes naked, when none of mA, vol or pull
@@ -165,4 +179,5 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad);
  */
 int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
 
+#endif /* __ASSEMBLY__ */
 #endif /* __MACH_MXS_IOMUX_H__*/