Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / arm / include / asm / arch-omap5 / clock.h

diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index f7ddd5ffe51db6e4d538aabbef28641c967583b9..4d2765d878f0be40215f0d4449bf66d42b819e46 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -81,7 +81,7 @@
 #define CM_CLKSEL_DCC_EN_MASK                  (1 << 22)
 
 /* CM_SYS_CLKSEL */
-#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
 
 /* CM_CLKSEL_CORE */
 #define CLKSEL_CORE_SHIFT      0
@@ -98,6 +98,12 @@
 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK    0
 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK    1
 
+/* CM_CLKSEL_ABE_PLL_SYS */
+#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT     0
+#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK      1
+#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1          0
+#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2          1
+
 /* CM_BYPCLK_DPLL_IVA */
 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT                0
 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK         3
@@ -219,6 +225,36 @@
 #define VDD_CORE_DRA752                1030
 #define VDD_IVA_DRA752         1060
 
+/* Efuse register offsets for DRA7xx platform */
+#define DRA752_EFUSE_BASE      0x4A002000
+#define DRA752_EFUSE_REGBITS   16
+/* STD_FUSE_OPP_VMIN_IVA_2 */
+#define STD_FUSE_OPP_VMIN_IVA_NOM      (DRA752_EFUSE_BASE + 0x05CC)
+/* STD_FUSE_OPP_VMIN_IVA_3 */
+#define STD_FUSE_OPP_VMIN_IVA_OD       (DRA752_EFUSE_BASE + 0x05D0)
+/* STD_FUSE_OPP_VMIN_IVA_4 */
+#define STD_FUSE_OPP_VMIN_IVA_HIGH     (DRA752_EFUSE_BASE + 0x05D4)
+/* STD_FUSE_OPP_VMIN_DSPEVE_2 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_NOM   (DRA752_EFUSE_BASE + 0x05E0)
+/* STD_FUSE_OPP_VMIN_DSPEVE_3 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_OD    (DRA752_EFUSE_BASE + 0x05E4)
+/* STD_FUSE_OPP_VMIN_DSPEVE_4 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH  (DRA752_EFUSE_BASE + 0x05E8)
+/* STD_FUSE_OPP_VMIN_CORE_2 */
+#define STD_FUSE_OPP_VMIN_CORE_NOM     (DRA752_EFUSE_BASE + 0x05F4)
+/* STD_FUSE_OPP_VMIN_GPU_2 */
+#define STD_FUSE_OPP_VMIN_GPU_NOM      (DRA752_EFUSE_BASE + 0x1B08)
+/* STD_FUSE_OPP_VMIN_GPU_3 */
+#define STD_FUSE_OPP_VMIN_GPU_OD       (DRA752_EFUSE_BASE + 0x1B0C)
+/* STD_FUSE_OPP_VMIN_GPU_4 */
+#define STD_FUSE_OPP_VMIN_GPU_HIGH     (DRA752_EFUSE_BASE + 0x1B10)
+/* STD_FUSE_OPP_VMIN_MPU_2 */
+#define STD_FUSE_OPP_VMIN_MPU_NOM      (DRA752_EFUSE_BASE + 0x1B20)
+/* STD_FUSE_OPP_VMIN_MPU_3 */
+#define STD_FUSE_OPP_VMIN_MPU_OD       (DRA752_EFUSE_BASE + 0x1B24)
+/* STD_FUSE_OPP_VMIN_MPU_4 */
+#define STD_FUSE_OPP_VMIN_MPU_HIGH     (DRA752_EFUSE_BASE + 0x1B28)
+
 /* Standard offset is 0.5v expressed in uv */
 #define PALMAS_SMPS_BASE_VOLT_UV 500000
 
@@ -245,6 +281,11 @@
 #define TPS62361_BASE_VOLT_MV  500
 #define TPS62361_VSEL0_GPIO    7
 
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0           0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ     500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ       1000
+
 #define DPLL_NO_LOCK   0
 #define DPLL_LOCK      1
 
@@ -254,4 +295,25 @@
  * into microsec and passing the value.
  */
 #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC        31219
+
+#ifdef CONFIG_DRA7XX
+#define V_OSCK                 20000000        /* Clock output from T2 */
+#else
+#define V_OSCK                 19200000        /* Clock output from T2 */
+#endif
+
+#define V_SCLK V_OSCK
+
+/* AUXCLKx reg fields */
+#define AUXCLK_ENABLE_MASK             (1 << 8)
+#define AUXCLK_SRCSELECT_SHIFT         1
+#define AUXCLK_SRCSELECT_MASK          (3 << 1)
+#define AUXCLK_CLKDIV_SHIFT            16
+#define AUXCLK_CLKDIV_MASK             (0xF << 16)
+
+#define AUXCLK_SRCSELECT_SYS_CLK       0
+#define AUXCLK_SRCSELECT_CORE_DPLL     1
+#define AUXCLK_SRCSELECT_PER_DPLL      2
+#define AUXCLK_SRCSELECT_ALTERNATE     3
+
 #endif /* _CLOCKS_OMAP5_H_ */