Update from 2013.01 to 2013.07

[karo-tx-uboot.git] / arch / arm / include / asm / arch-omap5 / cpu.h

diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 5e62013236eb49cfcf39f8e5996ab45b1a7a67dd..3de598494848e3602c40cf44b041d00b81334f3b 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -4,24 +4,7 @@
  *
  *     Aneesh V <aneesh@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _CPU_H
@@ -119,18 +102,6 @@ struct watchdog {
 #define WD_UNLOCK1             0xAAAA
 #define WD_UNLOCK2             0x5555
 
-#define SYSCLKDIV_1            (0x1 << 6)
-#define SYSCLKDIV_2            (0x1 << 7)
-
-#define CLKSEL_GPT1            (0x1 << 0)
-
-#define EN_GPT1                        (0x1 << 0)
-#define EN_32KSYNC             (0x1 << 2)
-
-#define ST_WDT2                        (0x1 << 5)
-
-#define RESETDONE              (0x1 << 0)
-
 #define TCLR_ST                        (0x1 << 0)
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
@@ -142,6 +113,8 @@ struct watchdog {
 #define I2C_BASE1              (OMAP54XX_L4_PER_BASE + 0x70000)
 #define I2C_BASE2              (OMAP54XX_L4_PER_BASE + 0x72000)
 #define I2C_BASE3              (OMAP54XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4              (OMAP54XX_L4_PER_BASE + 0x7A000)
+#define I2C_BASE5              (OMAP54XX_L4_PER_BASE + 0x7C000)
 
 /* MUSB base */
 #define MUSB_BASE              (OMAP54XX_L4_CORE_BASE + 0xAB000)