Update from 2013.01 to 2013.07

[karo-tx-uboot.git] / arch / arm / include / asm / arch-tegra / tegra.h

diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 6d2e62f5594a4ae4ab72eddad8f4bdcf3196b0a7..25d1fc4db1dd3a1133f59d4b244248e4880d5579 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -2,23 +2,7 @@
  * (C) Copyright 2010,2011
  * NVIDIA Corporation <www.nvidia.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _TEGRA_H_
@@ -40,6 +24,12 @@
 #define NV_PA_APB_UARTE_BASE   (NV_PA_APB_MISC_BASE + 0x6400)
 #define NV_PA_NAND_BASE                (NV_PA_APB_MISC_BASE + 0x8000)
 #define NV_PA_SPI_BASE         (NV_PA_APB_MISC_BASE + 0xC380)
+#define NV_PA_SLINK1_BASE      (NV_PA_APB_MISC_BASE + 0xD400)
+#define NV_PA_SLINK2_BASE      (NV_PA_APB_MISC_BASE + 0xD600)
+#define NV_PA_SLINK3_BASE      (NV_PA_APB_MISC_BASE + 0xD800)
+#define NV_PA_SLINK4_BASE      (NV_PA_APB_MISC_BASE + 0xDA00)
+#define NV_PA_SLINK5_BASE      (NV_PA_APB_MISC_BASE + 0xDC00)
+#define NV_PA_SLINK6_BASE      (NV_PA_APB_MISC_BASE + 0xDE00)
 #define TEGRA_DVC_BASE         (NV_PA_APB_MISC_BASE + 0xD000)
 #define NV_PA_PMC_BASE         (NV_PA_APB_MISC_BASE + 0xE400)
 #define NV_PA_EMC_BASE         (NV_PA_APB_MISC_BASE + 0xF400)
@@ -66,20 +56,32 @@ struct timerus {
 
 /* These are the available SKUs (product types) for Tegra */
 enum {
+       SKU_ID_T20_7            = 0x7,
        SKU_ID_T20              = 0x8,
        SKU_ID_T25SE            = 0x14,
        SKU_ID_AP25             = 0x17,
        SKU_ID_T25              = 0x18,
        SKU_ID_AP25E            = 0x1b,
        SKU_ID_T25E             = 0x1c,
+       SKU_ID_T33              = 0x80,
+       SKU_ID_T30              = 0x81, /* Cardhu value */
+       SKU_ID_T114_ENG         = 0x00, /* Dalmore value, unfused */
+       SKU_ID_T114_1           = 0x01,
 };
 
-/* These are the SOC categories that affect clocking */
+/*
+ * These are used to distinguish SOC types for setting up clocks. Mostly
+ * we can tell the clocking required by looking at the SOC sku_id, but
+ * for T30 it is a user option as to whether to run PLLP in fast or slow
+ * mode, so we have two options there.
+ */
 enum {
        TEGRA_SOC_T20,
        TEGRA_SOC_T25,
+       TEGRA_SOC_T30,
+       TEGRA_SOC_T114,
 
-       TEGRA_SOC_COUNT,
+       TEGRA_SOC_CNT,
        TEGRA_SOC_UNKNOWN       = -1,
 };