Update from 2013.01 to 2013.07

[karo-tx-uboot.git] / arch / arm / include / asm / arch-tegra20 / usb.h

diff --git a/arch/arm/include/asm/arch-tegra20/usb.h b/arch/arm/include/asm/arch-tegra20/usb.h
index fdbd127e6c00c15546f8dc5da14c332bc347657a..3d94cc73b8bf2b355ffdf64931402ae1d00acc01 100644 (file)
--- a/arch/arm/include/asm/arch-tegra20/usb.h
+++ b/arch/arm/include/asm/arch-tegra20/usb.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -19,9 +20,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _TEGRA_USB_H_
-#define _TEGRA_USB_H_
-
+#ifndef _TEGRA20_USB_H_
+#define _TEGRA20_USB_H_
 
 /* USB Controller (USBx_CONTROLLER_) regs */
 struct usb_ctlr {
@@ -135,17 +135,6 @@ struct usb_ctlr {
        uint utmip_bias_cfg1;
 };
 
-
-/* USB1_LEGACY_CTRL */
-#define USB1_NO_LEGACY_MODE            1
-
-#define VBUS_SENSE_CTL_SHIFT                   1
-#define VBUS_SENSE_CTL_MASK                    (3 << VBUS_SENSE_CTL_SHIFT)
-#define VBUS_SENSE_CTL_VBUS_WAKEUP             0
-#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP      1
-#define VBUS_SENSE_CTL_AB_SESS_VLD             2
-#define VBUS_SENSE_CTL_A_SESS_VLD              3
-
 /* USB2_IF_ULPI_TIMING_CTRL_0 */
 #define ULPI_OUTPUT_PINMUX_BYP                 (1 << 10)
 #define ULPI_CLKOUT_PINMUX_BYP                 (1 << 11)
@@ -158,114 +147,9 @@ struct usb_ctlr {
 #define ULPI_DIR_TRIMMER_LOAD                  (1 << 24)
 #define ULPI_DIR_TRIMMER_SEL(x)                        (((x) & 0x7) << 25)
 
-/* USBx_IF_USB_SUSP_CTRL_0 */
-#define ULPI_PHY_ENB                           (1 << 13)
-#define UTMIP_PHY_ENB                          (1 << 12)
-#define UTMIP_RESET                            (1 << 11)
-#define USB_PHY_CLK_VALID                      (1 << 7)
-#define USB_SUSP_CLR                           (1 << 5)
-
-/* USBx_UTMIP_MISC_CFG1 */
-#define UTMIP_PLLU_STABLE_COUNT_SHIFT          6
-#define UTMIP_PLLU_STABLE_COUNT_MASK           \
-                               (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
-#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT       18
-#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK                \
-                               (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
-#define UTMIP_PHY_XTAL_CLOCKEN                 (1 << 30)
-
-/* USBx_UTMIP_PLL_CFG1_0 */
-#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT      27
-#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK       \
-                               (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
-#define UTMIP_XTAL_FREQ_COUNT_SHIFT            0
-#define UTMIP_XTAL_FREQ_COUNT_MASK             0xfff
-
-/* USBx_UTMIP_BIAS_CFG1_0 */
-#define UTMIP_BIAS_PDTRK_COUNT_SHIFT           3
-#define UTMIP_BIAS_PDTRK_COUNT_MASK            \
-                               (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
-
-#define UTMIP_DEBOUNCE_CFG0_SHIFT              0
-#define UTMIP_DEBOUNCE_CFG0_MASK               0xffff
-
-/* USBx_UTMIP_TX_CFG0_0 */
-#define UTMIP_FS_PREAMBLE_J                    (1 << 19)
-
-/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
-#define UTMIP_PD_CHRG                          1
-
-/* USBx_UTMIP_XCVR_CFG0_0 */
-#define UTMIP_XCVR_LSBIAS_SE                   (1 << 21)
-
-/* USBx_UTMIP_SPARE_CFG0_0 */
-#define FUSE_SETUP_SEL                         (1 << 3)
-
-/* USBx_UTMIP_HSRX_CFG0_0 */
-#define UTMIP_IDLE_WAIT_SHIFT                  15
-#define UTMIP_IDLE_WAIT_MASK                   (0x1f << UTMIP_IDLE_WAIT_SHIFT)
-#define UTMIP_ELASTIC_LIMIT_SHIFT              10
-#define UTMIP_ELASTIC_LIMIT_MASK               \
-                               (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
-
-/* USBx_UTMIP_HSRX_CFG0_1 */
-#define UTMIP_HS_SYNC_START_DLY_SHIFT          1
-#define UTMIP_HS_SYNC_START_DLY_MASK           \
-                               (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT)
-
-/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
-#define IC_ENB1                                        (1 << 3)
-
-/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
-#define PTS_SHIFT                              30
-#define PTS_MASK                               (3U << PTS_SHIFT)
-#define PTS_UTMI               0
-#define PTS_RESERVED   1
-#define PTS_ULPI               2
-#define PTS_ICUSB_SER  3
-
-#define STS                                    (1 << 29)
-#define WKOC                           (1 << 22)
-#define WKDS                           (1 << 21)
-#define WKCN                           (1 << 20)
-
-/* USBx_UTMIP_XCVR_CFG0_0 */
-#define UTMIP_FORCE_PD_POWERDOWN               (1 << 14)
-#define UTMIP_FORCE_PD2_POWERDOWN              (1 << 16)
-#define UTMIP_FORCE_PDZI_POWERDOWN             (1 << 18)
-
-/* USBx_UTMIP_XCVR_CFG1_0 */
-#define UTMIP_FORCE_PDDISC_POWERDOWN           (1 << 0)
-#define UTMIP_FORCE_PDCHRP_POWERDOWN           (1 << 2)
-#define UTMIP_FORCE_PDDR_POWERDOWN             (1 << 4)
-
-/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
-#define VBUS_VLD_STS                   (1 << 26)
-
-
-/* Change the USB host port into host mode */
-void usb_set_host_mode(void);
-
-/* Setup USB on the board */
-int board_usb_init(const void *blob);
-
-/**
- * Start up the given port number (ports are numbered from 0 on each board).
- * This returns values for the appropriate hccr and hcor addresses to use for
- * USB EHCI operations.
- *
- * @param portnum      port number to start
- * @param hccr         returns start address of EHCI HCCR registers
- * @param hcor         returns start address of EHCI HCOR registers
- * @return 0 if ok, -1 on error (generally invalid port number)
- */
-int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor);
-
-/**
- * Stop the current port
- *
- * @return 0 if ok, -1 if no port was active
- */
-int tegrausb_stop_port(int portnum);
+/* PORTSC, USB2, USB3 */
+#define PTS_SHIFT              30
+#define PTS_MASK               (3U << PTS_SHIFT)
 
-#endif /* _TEGRA_USB_H_ */
+#define STS                    (1 << 29)
+#endif /* _TEGRA20_USB_H_ */