*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MACH_IOMUX_V3_H__
#define __MACH_IOMUX_V3_H__
+#include <common.h>
+
/*
* build IOMUX_PAD structure
*
#define MUX_SEL_INPUT_SHIFT 59
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
+#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
+ MUX_MODE_SHIFT)
#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
+#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
+ MUX_PAD_CTRL(pad))
+
+#define __NA_ 0x000
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+
#define NO_PAD_CTRL (1 << 17)
+
+#ifdef CONFIG_MX6
+
+#define PAD_CTL_HYS (1 << 16)
+
+#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE)
+#define PAD_CTL_PKE (1 << 12)
+
+#define PAD_CTL_ODE (1 << 11)
+
+#define PAD_CTL_SPEED_LOW (1 << 6)
+#define PAD_CTL_SPEED_MED (2 << 6)
+#define PAD_CTL_SPEED_HIGH (3 << 6)
+
+#define PAD_CTL_DSE_DISABLE (0 << 3)
+#define PAD_CTL_DSE_240ohm (1 << 3)
+#define PAD_CTL_DSE_120ohm (2 << 3)
+#define PAD_CTL_DSE_80ohm (3 << 3)
+#define PAD_CTL_DSE_60ohm (4 << 3)
+#define PAD_CTL_DSE_48ohm (5 << 3)
+#define PAD_CTL_DSE_40ohm (6 << 3)
+#define PAD_CTL_DSE_34ohm (7 << 3)
+
+#if defined CONFIG_MX6SL
+#define PAD_CTL_LVE (1 << 1)
+#define PAD_CTL_LVE_BIT (1 << 22)
+#endif
+
+#elif defined(CONFIG_VF610)
+
+#define PAD_MUX_MODE_SHIFT 20
+
+#define PAD_CTL_SPEED_MED (1 << 12)
+#define PAD_CTL_SPEED_HIGH (3 << 12)
+
+#define PAD_CTL_DSE_150ohm (1 << 6)
+#define PAD_CTL_DSE_50ohm (3 << 6)
+#define PAD_CTL_DSE_25ohm (6 << 6)
+#define PAD_CTL_DSE_20ohm (7 << 6)
+
+#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PKE (1 << 3)
+#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
+
+#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
+
+#else
+
+#define PAD_CTL_DVS (1 << 13)
+#define PAD_CTL_INPUT_DDR (1 << 9)
+#define PAD_CTL_HYS (1 << 8)
+
+#define PAD_CTL_PKE (1 << 7)
+#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
+
+#define PAD_CTL_ODE (1 << 3)
+
+#define PAD_CTL_DSE_LOW (0 << 1)
+#define PAD_CTL_DSE_MED (1 << 1)
+#define PAD_CTL_DSE_HIGH (2 << 1)
+#define PAD_CTL_DSE_MAX (3 << 1)
+
+#endif
+
+#define PAD_CTL_SRE_SLOW (0 << 0)
+#define PAD_CTL_SRE_FAST (1 << 0)
+
+#define IOMUX_CONFIG_SION 0x10
+
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_SHIFT 5
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-#define MUX_CONFIG_SION (0x1 << 4)
-
-int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
-
-/*
- * IOMUXC_GPR13 bit fields
- */
-#define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30)
-#define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29)
-#define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28)
-#define IOMUXC_GPR13_ENET_STOP_REQ (1<<27)
-#define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24)
-#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19)
-#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16
-#define IOMUXC_GPR13_SATA_PHY_6_MASK (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
-#define IOMUXC_GPR13_SATA_SPEED_MASK (1<<15)
-#define IOMUXC_GPR13_SATA_PHY_5_MASK (1<<14)
-#define IOMUXC_GPR13_SATA_PHY_4_MASK (7<<11)
-#define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f<<7)
-#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2)
-#define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0)
-
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111<<24)
-
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19)
-
-#define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15)
-#define IOMUXC_GPR13_SATA_SPEED_3G (1<<15)
-
-#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0<<14)
-#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1<<14)
-
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0<<11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1<<11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2<<11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3<<11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11)
-
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111<<7)
-
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111<<2)
-
-#define IOMUXC_GPR13_SATA_PHY_1_FAST 0
-#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
-#define IOMUXC_GPR13_SATA_PHY_1_SLOW 2
-
-#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
- |IOMUXC_GPR13_SATA_PHY_7_MASK \
- |IOMUXC_GPR13_SATA_PHY_6_MASK \
- |IOMUXC_GPR13_SATA_SPEED_MASK \
- |IOMUXC_GPR13_SATA_PHY_5_MASK \
- |IOMUXC_GPR13_SATA_PHY_4_MASK \
- |IOMUXC_GPR13_SATA_PHY_3_MASK \
- |IOMUXC_GPR13_SATA_PHY_2_MASK \
- |IOMUXC_GPR13_SATA_PHY_1_MASK)
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+ unsigned count);
+
+/* macros for declaring and using pinmux array */
+#if defined(CONFIG_MX6QDL)
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
+#define SETUP_IOMUX_PAD(def) \
+if (is_cpu_type(MXC_CPU_MX6Q)) { \
+ imx_iomux_v3_setup_pad(MX6Q_##def); \
+} else { \
+ imx_iomux_v3_setup_pad(MX6DL_##def); \
+}
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#define IOMUX_PADS(x) MX6Q_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6Q_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#else
+#define IOMUX_PADS(x) MX6DL_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6DL_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#endif
#endif /* __MACH_IOMUX_V3_H__*/
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