-#ifndef CONFIG_SOC_K2E
- } else if (data->pll == TETRIS_PLL) {
- bwadj = pllm >> 1;
- /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
- setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- /*
- * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
- * only applicable for Kepler
- */
- clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
- /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
- setbits_le32(keystone_pll_regs[data->pll].reg1 ,
- PLL_PLLRST | PLLCTL_ENSAT);
-
- /*
- * 3 Program PLLM and PLLD in PLLCTL0 register
- * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
- * PLLCTL1 register. BWADJ value must be set
- * to ((PLLM + 1) >> 1) – 1)
- */
- tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
- (pllm << 6) |
- (plld & PLL_DIV_MASK) |
- (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
-
- /* Set BWADJ[11:8] bits */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
- tmp &= ~(PLL_BWADJ_HI_MASK);
- tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
- /*
- * 5 Wait for at least 5 us based on the reference
- * clock (PLL reset time)
- */
- sdelay(21000); /* Wait for a minimum of 7 us*/
-
- /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
- clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
- /*
- * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
- * (PLL lock time)
- */
- sdelay(105000);
- /* 8 disable bypass */
- clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- /*
- * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
- * only applicable for Kepler
- */
- setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
-#endif
- } else {
- setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
- /*
- * process keeps state of Bypass bit while programming
- * all other DDR PLL settings
- */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
- tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */