ARM: keystone2: Cleanup PLL init code

[karo-tx-uboot.git] / arch / arm / mach-keystone / include / mach / clock_defs.h

diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h
index 85a046b89a92c11620512795cbb5210cb97eaa07..1c9dc3e7450271c63066ea2ff8cd53da1216a315 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/clock_defs.h
+++ b/arch/arm/mach-keystone/include/mach/clock_defs.h
@@ -69,7 +69,6 @@ static struct pllctl_regs *pllctl_regs[] = {
 
 #define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
 
-/* PLLCTL Bits */
 #define PLLCTL_BYPASS           BIT(23)
 #define PLL_PLLRST              BIT(14)
 #define PLLCTL_PAPLL            BIT(13)
@@ -102,10 +101,67 @@ static struct pllctl_regs *pllctl_regs[] = {
 #define PLL_BWADJ_LO_SMASK      (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
 #define PLL_BWADJ_HI_MASK       0xf
 
-#define PLLM_RATIO_DIV1         (PLLDIV_ENABLE | 0x0)
-#define PLLM_RATIO_DIV2         (PLLDIV_ENABLE | 0x0)
-#define PLLM_RATIO_DIV3         (PLLDIV_ENABLE | 0x1)
-#define PLLM_RATIO_DIV4         (PLLDIV_ENABLE | 0x4)
-#define PLLM_RATIO_DIV5         (PLLDIV_ENABLE | 0x17)
+/* PLLCTL Bits */
+#define PLLCTL_PLLENSRC_SHIF   5
+#define PLLCTL_PLLENSRC_MASK   BIT(5)
+#define PLLCTL_PLLRST_SHIFT    3
+#define PLLCTL_PLLRST_MASK     BIT(3)
+#define PLLCTL_PLLPWRDN_SHIFT  1
+#define PLLCTL_PLLPWRDN_MASK   BIT(1)
+#define PLLCTL_PLLEN_SHIFT     0
+#define PLLCTL_PLLEN_MASK      BIT(0)
+
+/* SECCTL Bits */
+#define SECCTL_BYPASS_SHIFT    23
+#define SECCTL_BYPASS_MASK     BIT(23)
+#define SECCTL_OP_DIV_SHIFT    19
+#define SECCTL_OP_DIV_MASK     (0xf << 19)
+
+/* PLLM Bits */
+#define PLLM_MULT_LO_SHIFT     0
+#define PLLM_MULT_LO_MASK      0x3f
+#define PLLM_MULT_LO_BITS      6
+
+/* PLLDIVn Bits */
+#define PLLDIV_ENABLE_SHIFT    15
+#define PLLDIV_ENABLE_MASK     BIT(15)
+#define PLLDIV_RATIO_SHIFT     0x0
+#define PLLDIV_RATIO_MASK      0xff
+#define PLLDIV_MAX             16
+
+/* PLLCMD Bits */
+#define PLLCMD_GOSET_SHIFT     0
+#define PLLCMD_GOSET_MASK      BIT(0)
+
+/* PLLSTAT Bits */
+#define PLLSTAT_GOSTAT_SHIFT   0
+#define PLLSTAT_GOSTAT_MASK    BIT(0)
+
+/* Device Config PLLCTL0 */
+#define CFG_PLLCTL0_BWADJ_SHIFT                24
+#define CFG_PLLCTL0_BWADJ_MASK         (0xff << 24)
+#define CFG_PLLCTL0_BWADJ_BITS         8
+#define CFG_PLLCTL0_BYPASS_SHIFT       23
+#define CFG_PLLCTL0_BYPASS_MASK                BIT(23)
+#define CFG_PLLCTL0_CLKOD_SHIFT                19
+#define CFG_PLLCTL0_CLKOD_MASK         (0xf << 19)
+#define CFG_PLLCTL0_PLLM_HI_SHIFT      12
+#define CFG_PLLCTL0_PLLM_HI_MASK       (0x7f << 12)
+#define CFG_PLLCTL0_PLLM_SHIFT         6
+#define CFG_PLLCTL0_PLLM_MASK          (0x1fff << 6)
+#define CFG_PLLCTL0_PLLD_SHIFT         0
+#define CFG_PLLCTL0_PLLD_MASK          0x3f
+
+/* Device Config PLLCTL1 */
+#define CFG_PLLCTL1_RST_SHIFT  14
+#define CFG_PLLCTL1_RST_MASK   BIT(14)
+#define CFG_PLLCTL1_PAPLL_SHIFT        13
+#define CFG_PLLCTL1_PAPLL_MASK BIT(13)
+#define CFG_PLLCTL1_ENSAT_SHIFT        6
+#define CFG_PLLCTL1_ENSAT_MASK BIT(6)
+#define CFG_PLLCTL1_BWADJ_SHIFT        0
+#define CFG_PLLCTL1_BWADJ_MASK 0xf
+
+#define MISC_CTL1_ARM_PLL_EN   BIT(13)
 
 #endif  /* _CLOCK_DEFS_H_ */