#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
-#define RA t8
+#define RA t9
/*
* 16kB is the maximum size of instruction and data caches on MIPS 4K,
move RA, ra
li t2, CONFIG_SYS_ICACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
- li t4, CONFIG_SYS_CACHELINE_SIZE
+ li t8, CONFIG_SYS_CACHELINE_SIZE
li v0, MIPS_MAX_CACHE_SIZE
* Initialize the I-cache first,
*/
move a1, t2
- move a2, t4
- PTR_LA t7, mips_init_icache
- jalr t7
+ move a2, t8
+ PTR_LA v1, mips_init_icache
+ jalr v1
/*
* then initialize D-cache.
*/
move a1, t3
- move a2, t4
- PTR_LA t7, mips_init_dcache
- jalr t7
+ move a2, t8
+ PTR_LA v1, mips_init_dcache
+ jalr v1
jr RA
END(mips_cache_reset)